syslib.c

ixp2400 bsp for vxworks

/* sysLib.c - ixdp2400 Board Specific routines */

/* Copyright 2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01c,14jan03,scm  wrap aduc812Init with #if defined (INCLUDE_PCI)...
01b,22oct02,scm  replace LOCAL_MEM_RESERVED with USER_RESERVED_MEM
01a,05apr,vgd  created form brh bsp
*/

/*
DESCRIPTION
This library provides board-specific routines.

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "stdio.h"
#include "usrLib.h"
#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"

#include "logLib.h"
#include "errnoLib.h"

#include "bootLib.h"
#include "vme.h"
#include "in.h"
#include "memLib.h"
#include "cacheLib.h"
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"

#if defined(INCLUDE_PCI)
#include "ixdp2400Pci.h"
#include "pciIomapLib.h"
#endif

void * sysVirtToPhys(void *virtAddr);
void * sysPhysToVirt(void *physAddr);

void sysMemVirtSize(unsigned int* sys, 
                    unsigned int* sys_all, 
                    unsigned int* sdram,
                    unsigned int* sram,
                    unsigned int* sram0, 
                    unsigned int* sram1,
                    unsigned int* sram2,
                    unsigned int* sram3, 
                    unsigned int* flash);


void sysLEDDisplay(unsigned char c1,unsigned char c2,unsigned char c3,unsigned char c4);
void * cacheDmaXMalloc(size_t bytes);

extern void dcacheOn(void);
extern void dcacheOff(void);
extern void dcacheSync(void);
extern void dcacheFlush(void);
extern unsigned int getCP15(void);




#include "ixdp2400IntrCtl.c"
#include "ixdp2400Timer.c"

#if defined(INCLUDE_SERIAL)
#include "sysSerial.c"
#include "ixdp2400Sio.c"
#endif

#if defined(INCLUDE_PCI)
#include "ixdp2400Pci.c"
#include "pciIomapLib.c"
#include "pciIomapShow.c"
#include "sysEnd.c"
#include "aduc812.c"
#endif


#include "ixdp2400I2c.c"
#include "ixdp2400.c"
/* Source Drivers */
#ifdef INCLUDE_FLASH
#include "flashMem.c"
#include "mem/nvRamToFlash.c"
#else
#include "mem/nullNvRam.c"
#endif /* INCLUDE_FLASH */
/* retrieve auto-sized memory */
extern UINT32 sysPhysMemSize ();

/* externals */
IMPORT char end;                            /* end of system, created by ld */
IMPORT int      sysStartType;

IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */
IMPORT void sysIntStackSplit (char *, long);

/*These are needed specifically for the Application running on IXDP2400 
 * Platform and are not needed for a generic BSP
 */
IMPORT long __ashldi3 ();
IMPORT long __lshrdi3 ();

static void *func2 = __ashldi3;
static void *func =  __lshrdi3;

/*end of Application Specific stuff*/


IMPORT void romStart(int);



/* globals */
/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC or INCLUDE_MMU_FULL are
 * defined.
 *
 * The following are not the smallest areas that could be allocated for a
 * working system.  If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

#ifdef INCLUDE_HSI_PROBE
	{ /* 512 MB of physical high SDRAM mapped to virt 0x0 used by vxworks is cachable, */
    (void *) IXP2400_SDRAM_BASE_ADDR,   /* virtual address */
    (void *) IXP2400_SDRAM_BASE_ADDR,   /* physical address */
    SZ_512M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_BUFFERABLE
    },
#else
	{ /* 32 MB of physical high SDRAM mapped to virt 0x0 used by vxworks is cachable, */
    (void *) IXP2400_SDRAM_BASE_ADDR,   /* virtual address */
    (void *) SDRAM_HIGH_PHY,   /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_BUFFERABLE
    },
 	{ /* 480 MB Physical low SDRAM used by microengines*/
    (void *) SDRAM_HIGH_VIRT,        /* virtual address */
    (void *) IXP2400_SDRAM_BASE_ADDR,        /* physical address */
    SZ_480M,                                    /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
#endif
    { /*SRAM chan 0*/
    (void *) IXP2400_SRAM_CH0_BASE,             /* virtual address */
    (void *) IXP2400_SRAM_CH0_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },	
	{ /*SRAM BIT set operations ch 0*/
    (void *) IXDP2400_SRAM_CH0_BIT_SET_OPS_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CH0_BIT_SET_OPS_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },	
	 { /*SRAM chan 0 Bit Clr operation*/
    (void *) IXDP2400_SRAM_CH0_BIT_CLR_OPS_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CH0_BIT_CLR_OPS_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },	
	{ /*SRAM chan 0 ADD operation */
    (void *) IXDP2400_SRAM_CH0_ADD_OPS_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CH0_ADD_OPS_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },	
	{ /*SRAM chan 1*/
    (void *) IXP2400_SRAM_CH1_BASE,             /* virtual address */
    (void *) IXP2400_SRAM_CH1_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /*SRAM BIT set operations ch 1*/
    (void *) IXDP2400_SRAM_CH1_BIT_SET_OPS_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CH1_BIT_SET_OPS_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },	
	 { /*SRAM chan 1 Bit Clr operation*/
    (void *) IXDP2400_SRAM_CH1_BIT_CLR_OPS_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CH1_BIT_CLR_OPS_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },	
	{ /*SRAM chan 1 ADD operation */
    (void *) IXDP2400_SRAM_CH1_ADD_OPS_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CH1_ADD_OPS_BASE,             /* physical address */
    SZ_64M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },		
     { /* CAP csrs, non-cacheable, non-bufferable */
    (void *) IXP2400_CAP_BASE,             /* virtual address */
    (void *) IXP2400_CAP_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* FLASH */
    (void *) IXP2400_FLASH_BASE,             /* virtual address */
    (void *) IXP2400_FLASH_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* Media Slowport I/F 8MB */
    (void *) MEDIA_SLOWPORT_BASE,             /* virtual address */
    (void *) MEDIA_SLOWPORT_BASE,             /* physical address */
    SZ_8M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* MSF Slowport I/F 8MB */
    (void *) MSF_SLOWPORT_BASE,             /* virtual address */
    (void *) MSF_SLOWPORT_BASE,             /* physical address */
    SZ_8M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* CPLD CSRS*/
    (void *) CPLD_CSR_BASE,             /* virtual address */
    (void *) CPLD_CSR_BASE,             /* physical address */
    SZ_4K,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* MSF CSRS 16k */
    (void *) IXP2400_MSF_CSR_BASE,             /* virtual address */
    (void *) IXP2400_MSF_CSR_BASE,             /* physical address */
    SZ_16K,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* Scratch memory 32MB */
    (void *) IXP2400_SCRATCH_BASE,             /* virtual address */
    (void *) IXP2400_SCRATCH_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE
    },
 	{ /* SRAM CSR */
    (void *) IXDP2400_SRAM_CSR_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_CSR_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* SRAM RING */
    (void *) IXDP2400_SRAM_RING_BASE,             /* virtual address */
    (void *) IXDP2400_SRAM_RING_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE
    },
    { /* SDRAM / DDR CSRs */
    (void *) IXP2400_DDR_CNTRL_BASE,             /* virtual address */
    (void *) IXP2400_DDR_CNTRL_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
    { /* interrupt controller CSRs */
    (void *) IXP2400_INT_CTRL_BASE,             /* virtual address */
    (void *) IXP2400_INT_CTRL_BASE,             /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
#ifdef INCLUDE_PCI   
    { /* PCI CFG 0 Windows -non-cacheable, non-bufferable */
    (void *) PCI_CONFIG0_BASE,     /* virtual address */
    (void *) PCI_CONFIG0_BASE,     /* physical address */
    SZ_16M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
 	{ /* PCI and CFG 1 Windows -non-cacheable, non-bufferable */
    (void *) PCI_CONFIG1_BASE,     /* virtual address */
    (void *) PCI_CONFIG1_BASE,     /* physical address */
    SZ_16M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* PCI CFG CSR  Windows -non-cacheable, non-bufferable */
    (void *) IXP2400_PCI_CFG_REG_BASE,     /* virtual address */
    (void *) IXP2400_PCI_CFG_REG_BASE,     /* physical address */
    SZ_8K,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* PCI CSR  Windows -non-cacheable, non-bufferable */
    (void *) IXP2400_PCI_CSR_BASE,     /* virtual address */
    (void *) IXP2400_PCI_CSR_BASE,     /* physical address */
    SZ_8K,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* PCI I/O -non-cacheable, non-bufferable */
    (void *) 0xD8000000,     /* virtual address */
    (void *) 0xD8000000,     /* physical address */
    SZ_32M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
	{ /* PCI MEM SPACe -non-cacheable, non-bufferable */
    (void *) 0xE0000000,     /* virtual address */
    (void *) 0xE0000000,     /* physical address */
    SZ_512M,                                   /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE
    },
    /*  Allocate space for sysMmuMapAdd */
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0},
    {NULL, NULL, 0,0}        
#endif /*INCLUDE_PCI*/
   
};

int sysPhysMemDescNumEntMax = NELEMENTS (sysPhysMemDesc); 

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int  sysCpu = CPU;                   /* system CPU type */
char sysBootHost [BOOT_FIELD_LEN];   /* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN];   /* name of file from which we booted */
int  sysFlags;                       /* boot flags */

int sysProcNum = 0;                  /* processor number of this CPU */
char *sysBootLine = BOOT_LINE_ADRS;  /* address of boot line */

/* Area used to flush D-cache */
UINT32 sysCacheFlushReadArea[D_CACHE_SIZE/sizeof(UINT32)];

/* Area used to flush mini-cache */
UINT32 sysMinicacheFlushReadArea[MINI_CACHE_SIZE/sizeof(UINT32)];

char *sysExcMsg   = EXC_MSG_ADRS;    /* catastrophic message area */

UINT32 boardRev = 0;

UINT32 vxWorksTextAddr =0;

/*** Init Routines ***/
/******************************************************************************
*
* sysHwInit0 - Intialize _func_armVirtToPhys before sysHwInit is called
*
* This function initialized _func_armVirtToPhys and _func_armPhysToVirt
* before sysHwInit is called. It is called from usrInit in bootConfig.c
* before cacheLibInit is called.
*
* RETURNS: N/A
*/

void sysHwInit0()
    {
    sysLEDDisplay('S', 'Y', 'S','0');
#if defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU)
    /*
     * Install the appropriate cache libary, using the our
     * address translation routines.
     */
    cacheArmXSCALELibInstall(sysPhysToVirt, sysVirtToPhys);
#endif
#ifdef INCLUDE_MMU
    /* Install the appropriate MMU library and translation routines */
    mmuArmXSCALELibInstall (sysPhysToVirt, sysVirtToPhys);