ixdp2400.h

ixp2400 bsp for vxworks

#define RESET_XSCALE			1
#define RESET_SDRAM_SRAM		(RESET_DRAM0 | RESET_SRAM0 | RESET_SRAM1)
#define NOT_RESET_PCI			~(PCIRST | RESET_PCI)

#define IXP2400_PCI_CFG_REG_BASE	    0xDE000000 /* config register base */
#define IXP2400_PCI_CSR_BASE		    0xDF000000 /* Base of PCI Unit CSR's */

#define IXP2400_PCI_VENDOR_ID		    FIX_ADDR_16(IXP2400_PCI_CFG_REG_BASE + 0x000)
#define IXP2400_PCI_DEVICE_ID		    FIX_ADDR_16(IXP2400_PCI_CFG_REG_BASE + 0x002)
#define IXP2400_PCI_CMD_STAT			(IXP2400_PCI_CFG_REG_BASE + 0x004)
#define IXP2400_PCI_CACHE_LAT_HDR_BIST	(IXP2400_PCI_CFG_REG_BASE + 0x00C)
#define IXP2400_PCI_CSR_BAR             (IXP2400_PCI_CFG_REG_BASE + 0x010)
#define IXP2400_PCI_SRAM_BAR            (IXP2400_PCI_CFG_REG_BASE + 0x014)
#define IXP2400_PCI_DRAM_BAR            (IXP2400_PCI_CFG_REG_BASE + 0x018)
#define IXP2400_PCI_RCOMP_OVER			(IXP2400_PCI_CFG_REG_BASE + 0x060)
#define IXP2400_OUT_INT_STATUS          (IXP2400_PCI_CSR_BASE + 0x030)
#define IXP2400_OUT_INT_MASK            (IXP2400_PCI_CSR_BASE + 0x034)
#define IXP2400_PCI_INT_LAT             (IXP2400_PCI_CSR_BASE + 0x03c)
#define IXP2400_MAILBOX0                (IXP2400_PCI_CSR_BASE + 0x050)
#define IXP2400_MAILBOX1                (IXP2400_PCI_CSR_BASE + 0x054)
#define IXP2400_MAILBOX2                (IXP2400_PCI_CSR_BASE + 0x058)
#define IXP2400_MAILBOX3                (IXP2400_PCI_CSR_BASE + 0x05c)
#define IXP2400_DOORBELL                (IXP2400_PCI_CSR_BASE + 0x060)
#define IXP2400_DOORBELL_SETUP          (IXP2400_PCI_CSR_BASE + 0x064)
#define IXP2400_CHAN_1_BYTE_COUNT       (IXP2400_PCI_CSR_BASE + 0x080)
#define IXP2400_CHAN_1_PCI_BAR          (IXP2400_PCI_CSR_BASE + 0x084)
#define IXP2400_CHAN_1_DRAM_ADDR        (IXP2400_PCI_CSR_BASE + 0x088)
#define IXP2400_CHAN_1_DESC_PTR         (IXP2400_PCI_CSR_BASE + 0x08C)
#define IXP2400_CHAN_1_CONTROL          (IXP2400_PCI_CSR_BASE + 0x090)
#define IXP2400_DMA_INF_MODE            (IXP2400_PCI_CSR_BASE + 0x09C)
#define IXP2400_CHAN_2_BYTE_COUNT       (IXP2400_PCI_CSR_BASE + 0x0A0)
#define IXP2400_CHAN_2_PCI_BAR          (IXP2400_PCI_CSR_BASE + 0x0A4)
#define IXP2400_CHAN_2_DRAM_ADDR        (IXP2400_PCI_CSR_BASE + 0x0A8)
#define IXP2400_CHAN_2_DESC_PTR         (IXP2400_PCI_CSR_BASE + 0x0AC)
#define IXP2400_CHAN_2_CONTROL          (IXP2400_PCI_CSR_BASE + 0x0B0)
#define IXP2400_PCI_SRAM_BAR_MASK	    (IXP2400_PCI_CSR_BASE + 0x0FC)
#define IXP2400_DRAM_BASE_ADDR_MASK     (IXP2400_PCI_CSR_BASE + 0x100)
#define IXP2400_PCI_CONTROL             (IXP2400_PCI_CSR_BASE + 0x13C)
#define IXP2400_PCI_ADDR_EXT            (IXP2400_PCI_CSR_BASE + 0x140)
#define IXP2400_PCI_XSCALE_INT_ENABLE   (IXP2400_PCI_CSR_BASE + 0x15C)

#define IXP2400_PCI_XSCALE_INT_PILM	    (3 << 26)

#define IXP2400_PCI_CONTROL_XS_INT      (1 << 24) /* Enable the PCI INTA*/
#define IXP2400_PCI_CONTROL_BE_DEO      (1 << 22) /* PCI Big Endian Data Enable Out */
#define IXP2400_PCI_CONTROL_BE_DEI      (1 << 21) /* PCI Big Endian Data Enable In */
#define IXP2400_PCI_CONTROL_BE_BEO      (1 << 20) /* PCI Big Endian Byte Enable Out */
#define IXP2400_PCI_CONTROL_BE_BEI      (1 << 19) /* PCI Big Endian Byte Enable In */



#define IXP2400_PCI_CONTROL_PNR			(1 << 17) /* PCI Not Reset bit of SA_CONTROL */
#define IXP2400_PCI_CONTROL_CFG_RST_DIR (1 << 28) /* PCI Centrl Function bit */

/* 16 bit PCI registers */

#define IXP2400_PCI_COMMAND FIX_ADDR_16(IXP2400_PCI_CSR_BASE + 0x04)

/* Define PCI_COMMAND bits */

#define IO_SPACE_ENABLE				(1 << 0)
#define MEM_SPACE_ENABLE			(1 << 1)
#define BUS_MASTER_ENABLE			(1 << 2)
#define WR_INV_ENABLE				(1 << 4)
#define SERR_ENABLE					(1 << 8)
#define PCI_CMD_STAT_VAL			(BUS_MASTER_ENABLE | MEM_SPACE_ENABLE | IO_SPACE_ENABLE) /*vgd*/

#define XSIM	~(1 << 1)

#ifdef INCLUDE_PCI
/*
 * PCI definitions
 * 
 * First, defines for generic pciIoMapLib.c code
 * 
 * Cache Line Size - in number of 32-bit words
 * It might be thought that we would set this to (_CACHE_ALIGN_SIZE/4), but,
 * in fact, the areas of memory mapped for use either by PCI I/O and
 * PCI Configuration  and the area of (ARM) memory used by the Ethernet
 * controller are marked as non-cacheable, so we should set it to zero.
 */

#define PCI_CLINE_SZ    0

/*
 * Latency Timer value
 * A sensible value for this depends what we are using PCI for.
 * (Rather arbitrarily) leave it at 0 (the reset default value)
 */

#define PCI_LAT_TIMER           0x0

#define SWAP16(x) 				((((x) << 8) | ((x) >> 8)) & 0xFFFF)
#define SWAP32(x)				(((x) << 24) |                \
	                            (((x) & 0x0000FF00) << 8) |   \
                                (((x) & 0x00FF0000) >> 8) |   \
                                (((unsigned int)(x)) >> 24))

/*
 * Dummy interrupt number for pciIntConnect(): must be passed a real
 * interrupt vector number. This allows for non-linear mappings
 * between interrupts, slots etc.
 */

#define INT_NUM_IRQ0    0

/* memory map as seen by the CPU on the local bus */
#ifdef INCLUDE_EXTRA_PCI_MAPPING
#define CPU_PCI_MEM_ADRS    PCI_MEM_BASE /* PCI memory space base */
#define CPU_PCI_MEM_SIZE    0x20000000   /* 512 Mbytes */
#endif

#define CPU_PCI_IO_ADRS     PCI_IO_BASE  /* PCI I/O space base */
#define CPU_PCI_IO_SIZE     0x2000000    /* 32 Mbytes */

#define CPU_PCI_CNFG_ADRS   PCI_CONFIG0_BASE  /* type 0 PCI config space */
#define CPU_PCI_CNFG_SIZE   0x1000000         /* 16 Mbytes */

#define CPU_PCI_CNFG_1_ADRS PCI_CONFIG1_BASE  /* type 1 PCI config space */
#define CPU_PCI_CNFG_1_SIZE 0x1000000         /* 16 Mbytes */


/* PCI view of PCI I/O space for PCI devices */
#define PCI_IO_ADRS         0x00000000  /* base of PCI I/O address */

/* PCI bus resources */
#define PCI_IO_SIZE         0x80            /* PCI I/O size */

/* PCI device 0: slot I/O 4 */
#define PCI_MEM_ADR0        0x00            /* Memory base for CSR */
#define PCI_IO_ADR0         PCI_IO_ADRS     /* I/O base for CSR 32Bytes */
#define PCI_IO_SIZE0        PCI_IO_SIZE     /* I/O size for CSR */
#define PCI_INT_LVL0        INT_VEC_PIL     /* Interrupt level */
#define PCI_INT_VEC0        IVEC_TO_INUM(PCI_INT_LVL0) /* Interrupt vector */

/* PCI device 1: slot I/O 3 */
#define PCI_MEM_ADR1        0x00
#define PCI_IO_ADR1         PCI_IO_ADRS
#define PCI_IO_SIZE1        PCI_IO_SIZE
#define PCI_INT_LVL1        INT_VEC_PIL
#define PCI_INT_VEC1        IVEC_TO_INUM(PCI_INT_LVL1)

/* PCI device 2: slot I/O 2 */
#define PCI_MEM_ADR2        0x00
#define PCI_IO_ADR2         PCI_IO_ADRS
#define PCI_IO_SIZE2        PCI_IO_SIZE
#define PCI_INT_LVL2        INT_VEC_PIL
#define PCI_INT_VEC2        IVEC_TO_INUM(PCI_INT_LVL2)

/* PCI device 3: slot I/O 1 */
#define PCI_MEM_ADR3        0x00
#define PCI_IO_ADR3         PCI_IO_ADRS
#define PCI_IO_SIZE3        PCI_IO_SIZE
#define PCI_INT_LVL3        INT_VEC_PIL
#define PCI_INT_VEC3        IVEC_TO_INUM(PCI_INT_LVL3)

/*
 * N.B. Only the following values have been tested. In particular, no
 * testing has been performed with more than one PCI bus, i.e. Type 1
 * configuration.
*/

#define PCI_MAX_DEV     8
#define PCI_MAX_BUS     2       /* two bus */


/* Allocate Device Space (Offsets) for PCI devices */
#define LAN_DEV_SPACE       0
#define PCI_IO_LN_ADRS      (PCI_IO_ADRS + LAN_DEV_SPACE)


/* Allocated base address of h/w devices as seen from CPU */
#define LAN_BASE_ADRS       (CPU_PCI_IO_ADRS + LAN_DEV_SPACE)


/* Create configuration address */
#define MAKE_CFG_ADDR(bus, device, func, offset) ((bus) ? \
    ((UINT32)((bus & 0xFF) << 16) | (UINT32)((device & 0x1F) << 11) | \
     (UINT32)((func & 0x7) << 8)  | (UINT32) (offset & 0xFC)) : \
    ((UINT32)(1 << ((device & 0x1F) + 16)) | (UINT32)((func & 0x7) << 8) | \
     (UINT32) (offset & 0xFC)))
#endif /* ifdef INCLUDE_PCI */

 
/* slave's csr as seen from master */
#define SLAVE_GLOBAL_CONTROL_BASE	0x4A00

#define SLAVE_MISC_CONTROL			(SLAVE_GLOBAL_CONTROL_BASE + 0x4)
#define SLAVE_IXP_RESET0			(SLAVE_GLOBAL_CONTROL_BASE + 0xC)
#define SLAVE_CCR					(SLAVE_GLOBAL_CONTROL_BASE + 0x14)
#define SLAVE_STRAP_OPTIONS			(SLAVE_GLOBAL_CONTROL_BASE + 0x18)

#define SLAVE_SLOW_PORT_CSR_BASE	0x80000

#define SLAVE_SCRATCH_BASE			0xF0000

#define SLAVE_QDR_CH_BASE			0xF9000

#define SLAVE_DRAM_CH0_BASE			0xFD800

#define SLAVE_DU_CONTROL			(SLAVE_DRAM_CH0_BASE + 0x0)
#define SLAVE_DU_ECC_TEST			(SLAVE_DRAM_CH0_BASE + 0x18)
#define SLAVE_DU_INIT				(SLAVE_DRAM_CH0_BASE + 0x20)
#define SLAVE_DU_CONTROL2			(SLAVE_DRAM_CH0_BASE + 0x28)
#define SLAVE_DU_RCOMP_IO_CONFIG	(SLAVE_DRAM_CH0_BASE + 0x3C0)
#define SLAVE_DU_RDDLYSEL_RECEN		(SLAVE_DRAM_CH0_BASE + 0x3C8)
#define SLAVE_DU_RX_DLL				(SLAVE_DRAM_CH0_BASE + 0x650)
#define SLAVE_DU_RX_DESKEW			(SLAVE_DRAM_CH0_BASE + 0x688)



#define CR0_FRCSMRCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_FRCSMRCOMP_OFF)
#define CR0_DSTRENGTHSEL_FRM_PCI		(SLAVE_DRAM_CH0_BASE + CR0_DSTRENGTHSEL_OFF)
#define CR0_DDQRCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_DDQRCOMP_OFF)
#define CR0_DCTLRCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_DCTLRCOMP_OFF)
#define CR0_DRCVRCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_DRCVRCOMP_OFF)
#define CR0_DCKERCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_DCKERCOMP_OFF)
#define CR0_DCSRCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_DCSRCOMP_OFF)
#define CR0_DCKRCOMP_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_DCKRCOMP_OFF)
#define CR0_DX8X16CKECSCKSEL_FRM_PCI	(SLAVE_DRAM_CH0_BASE + CR0_DX8X16CKECSCKSEL_OFF)
#define CR0_RCOMPPRD_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_RCOMPPRD_OFF)
#define CR0_DIGFIL_FRM_PCI				(SLAVE_DRAM_CH0_BASE + CR0_DIGFIL_OFF)

#define CR0_SLEWPROGRAMMED_FRM_PCI		(SLAVE_DRAM_CH0_BASE + CR0_SLEWPROGRAMMED_OFF)
#define CR0_OVRRIDEH_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_OVRRIDEH_OFF)
#define CR0_OVRRIDEV_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_OVRRIDEV_OFF)
#define CR0_JT_CONFIG_FRM_PCI			(SLAVE_DRAM_CH0_BASE + CR0_JT_CONFIG_OFF)

#define SLAVE_PCI_CSR_BASE			0xFE000

#define SLAVE_PCI_OUT_INT_MASK		(SLAVE_PCI_CSR_BASE + 0x34)
#define SLAVE_MAILBOX_0				(SLAVE_PCI_CSR_BASE + 0x50)
#define SLAVE_PCI_CONTROL			(SLAVE_PCI_CSR_BASE + 0x13C)
#define SLAVE_PCI_ADDR_EXT			(SLAVE_PCI_CSR_BASE + 0x140)

#define BOOT_THRU_BM		        (1<<31) /*no boot monitor flag*/
#define BOOT_DONT_INIT_PCI          (1<<30)
#define BOOT_CMP_IMAGE				(1<<29)
#define BOOTROM_THRU_BM				(1<<28)


#define TB_VENDOR_ID				0x8086
#define TB_DEVICE_ID				0xB154

#define SDRAM_END		            0x20000000
#define SDRAM_HIGH_VIRT		        0x02000000
#define SDRAM_HIGH_PHY		        0x1e000000 

#define CONFIG_DATA_VALID	        0x12345678

/***** UART defines used in romInit****/

#ifdef CPU_SPEED_600MHZ
	#define BaudRateDivisor_115200     0x1B
	#define BaudRateDivisor_57600      0x36 
#else
	#define BaudRateDivisor_115200     0x12
	#define BaudRateDivisor_57600      0x24 
#endif


#define UARTLCR_DivisorLatchAccess 0x80
#define UART_LineControl           0x0C 
#define UART_DivisorLatchLSB       0x00	
#define UART_DivisorLatchMSB       0x04	
#define UARTLCR_CharLength8        0x03  
#define UARTLCR_StopBits1          0x00  
#define UART_InterruptEnable       0x04 
#define UARTFCR_Enable             (1<<0)
#define UART_FIFOControl           0x08
#define UARTFCR_RXReset            (1<<1)
#define ARTFCR_TXReset             (1<<2)
#define UARTFCR_Mode0RXRDYTXRDY    (0<<3)
#define UARTFCR_RXTrigger1         (0<<6)
#define UARTMCR_DTRActive          (1<<0)
#define UART_LineStatus            0x14
#define UART_Transmit              0x0
#define UART_Receive               0x0
#define UARTLSR_TXHoldingEmpty     (1<<5)
#define ROM_FIX_ADDR_MASK		   0x2fffffff


#define MMU_Control_M				0x200
#define MMU_Control_R  				0x001
#define MMU_Control_C  				0x004
#define MMU_Control_BTB 			0x800

#define ROM_MMU_TABLE_ADR			0xc4004000

#ifndef _ASMLANGUAGE
UINT32 slave_load_adrs;
#endif


#define SLAVE_LOAD_ADRS 			slave_load_adrs	

#define SLAVE_ENTRY_ADRS_LOW	(SDRAM_HIGH_PHY + RAM_LOW_ADRS +0x8000 )
#define SLAVE_ENTRY_ADRS_HI	(SDRAM_HIGH_PHY + RAM_HIGH_ADRS + 0x8000 )

#define BOOTROM_OFFSET		0xc4040000
#define BOOTROM_TEXT_ADRS	0xc4048000	
/* Assembly specific defs */
#ifndef _ASMLANGUAGE
#endif

#ifdef __cplusplus
}
#endif

#endif  /* INCIXDP2400h */