📄 ixdp2400.h

📁 ixp2400 bsp for vxworks
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#define T4_CTL   0x0C/*Timer Load Register offsets*/#define T1_CLD   0x10#define T2_CLD   0x14#define T3_CLD   0x18#define T4_CLD   0x1C/*Timer Status Register offsets*/#define T1_CSR   0x20#define T2_CSR   0x24#define T3_CSR   0x28#define T4_CSR   0x2C/*Timer Interupt Clear Register offsets*/#define T1_CLR   0x30#define T2_CLR   0x34#define T3_CLR   0x38#define T4_CLR   0x3C/*Timer Watch dog enable Register offsets*/#define TWDE     0x40/*Timer register addreses*/#define IXP2400_TIMER1_CONTROL	(IXP2400_TIMER_BASE + T1_CTL)#define IXP2400_TIMER2_CONTROL	(IXP2400_TIMER_BASE + T2_CTL)#define IXP2400_TIMER3_CONTROL	(IXP2400_TIMER_BASE + T3_CTL)#define IXP2400_TIMER4_CONTROL	(IXP2400_TIMER_BASE + T4_CTL)#define IXP2400_TIMER1_LOAD	    (IXP2400_TIMER_BASE + T1_CLD)#define IXP2400_TIMER2_LOAD	    (IXP2400_TIMER_BASE + T2_CLD)#define IXP2400_TIMER3_LOAD	    (IXP2400_TIMER_BASE + T3_CLD)#define IXP2400_TIMER4_LOAD	    (IXP2400_TIMER_BASE + T4_CLD)#define IXP2400_TIMER1_STATUS	(IXP2400_TIMER_BASE + T1_CSR)#define IXP2400_TIMER2_STATUS	(IXP2400_TIMER_BASE + T2_CSR)#define IXP2400_TIMER3_STATUS	(IXP2400_TIMER_BASE + T3_CSR)#define IXP2400_TIMER4_STATUS	(IXP2400_TIMER_BASE + T4_CSR)#define IXP2400_TIMER1_COUNTER_CLR	(IXP2400_TIMER_BASE + T1_CLR)#define IXP2400_TIMER2_COUNTER_CLR	(IXP2400_TIMER_BASE + T2_CLR)#define IXP2400_TIMER3_COUNTER_CLR	(IXP2400_TIMER_BASE + T3_CLR)#define IXP2400_TIMER4_COUNTER_CLR	(IXP2400_TIMER_BASE + T4_CLR)#define IXP2400_WATCHDOGTIMER_ENABLE	(IXP2400_TIMER_BASE + TWDE)/*timer register bits*/#define IXP2400_TIMER_INT_CLR	    0x01#define IXP2400_TIMER_ACTIVATE      0x80#define IXP2400_TIMER_PSS	        0x0#define IXP2400_TIMER_PSS_16        0x4#define IXP2400_TIMER_PSS_256       0x8#define IXP2400_TIMER_PSS_GPIO      0xc#define SYS_TIMER_CLK	ixp2400XtalFreq#define AUX_TIMER_CLK	ixp2400XtalFreq#undef RELOAD_TICKS#ifdef RELOAD_TICKS#define IXP2400_RELOAD_TICKS              10#endif#define TIMESTAMP_HZ	            SYS_TIMER_CLK		 /* timestamp counter freq */#define SYS_TIMER_INT_LVL 	        (IXP2400_INT_VEC_T2)#define AUX_TIMER_INT_LVL	        (IXP2400_INT_VEC_T3)#define TICKS_PER_USEC				(SYS_TIMER_CLK/1000000)/* Minimum rate at which the system clock can run */#define SYS_CLK_RATE_MIN                  0x1e/* 1000 ticks, Maximum rate at which the system clock can run */#define SYS_CLK_RATE_MAX                  0x3e8/* Minimum rate at which the auxiliary clock can run */#define AUX_CLK_RATE_MIN                  0x1e/* 1000 ticks, Maximum rate at which the auxiliary clock can run */#define AUX_CLK_RATE_MAX                  0x3e8/*--------------------------------------------------- * IXDP2400 INTERRUPTS... *--------------------------------------------------- */#define IXP2400_INT_CTRL_BASE	        0xd6000000#define IXP2400_IRQ_STATUS_REG          (IXP2400_INT_CTRL_BASE + 0x08)#define IXP2400_IRQ_ENABLE_SET_REG      (IXP2400_INT_CTRL_BASE + 0x10)#define IXP2400_IRQ_ENABLE_CLR_REG      (IXP2400_INT_CTRL_BASE + 0x18)#define IXP2400_INT_VEC_BASE            (0x0)#define IXP2400_INT_NUM_LEVELS          (32)#define IXP2400_INT_MAX_LEVELS          (32)#define IXP2400_INT_MODE                INT_NON_PREEMPT_MODEL#define IXP2400_MASK_ALL_INT            (0xffffffff)#define IXP2400_UNMASK_ALL_INT          (0x00000000)#define IXP2400_INT_ALL_ENABLED 32      /*all levels enabled*//*interrupt vectors*/#define IXP2400_INT_UART	            (2)#define INT_VEC_PIL		                (15)                  #define IXP2400_INT_VEC_T3              (6)	/* Timer 3 */ #define IXP2400_INT_VEC_T2              (5) /* Timer 2 */ #define CPLD_INGRESS_NPU_INT			0#define CPLD_NIC_INT					1#define CPLD_MEDIA_PCI_INT				2#define CPLD_MEDIA_SLOWPORT_INT			3#define CPLD_SF_PCI_INT					4#define CPLD_SF_SLOWPORT_INT			5#define CPLD_PMC_INT					6#define CPLD_ADUC_INT					7#define MAX_CPLD_INT					8/*--------------------------------------------------- * IXDP2400 FLASH... *--------------------------------------------------- */#define IXDP2400_BOOT_FLASH_ADDR          0xc4000000#define IXDP2400_BOOT_FLASH_SIZE          SZ_16M#define IXP2400_FLASH_BASE		          0xC4000000	/*--------------------------------------------------- *IXDP2400 SDRAM controller... *--------------------------------------------------- *//*SDRAM Starting Address */#define IXP2400_SDRAM_BASE_ADDR  0x00000000 /* SDRAM Address */#define IXP2400_SDRAM_SIZE		 256#define IXP2400_DDR_CNTRL_BASE	 0xD0009000#define IXP2400_DU_CONTROL		 (IXP2400_DDR_CNTRL_BASE + 0x000)#define IXP2400_DU_ECC_TEST		 (IXP2400_DDR_CNTRL_BASE + 0x018)#define IXP2400_DU_INIT			 (IXP2400_DDR_CNTRL_BASE + 0x020)#define IXP2400_DU_CONTROL2		 (IXP2400_DDR_CNTRL_BASE + 0x028)#define IXP2400_DDR_RDDLYSEL_RECEN	 (IXP2400_DDR_CNTRL_BASE +	0x3C8)#define IXP2400_DDR_RX_DLL			 (IXP2400_DDR_CNTRL_BASE +	0x650)#define IXP2400_DDR_RX_DESKEW		 (IXP2400_DDR_CNTRL_BASE +	0x688)#define DDR_RCOMP_IO_CONFIG			 (IXP2400_DDR_CNTRL_BASE +	0x3C0)#define DDR_RCOMP_IO_CONFIG_VAL		 0x0#define CR0_FRCSMRCOMP_OFF			0x100#define CR0_DSTRENGTHSEL_OFF		0x130#define CR0_DDQRCOMP_OFF			0x148#define CR0_DCTLRCOMP_OFF			0x190#define CR0_DRCVRCOMP_OFF			0x1D8#define CR0_DCKERCOMP_OFF			0x228#define CR0_DCSRCOMP_OFF			0x2B0#define CR0_DCKRCOMP_OFF			0x338#define CR0_DX8X16CKECSCKSEL_OFF	0x220#define CR0_RCOMPPRD_OFF			0x108#define CR0_DIGFIL_OFF				0x118#define CR0_SLEWPROGRAMMED_OFF		0x128#define CR0_OVRRIDEH_OFF			0x138#define CR0_OVRRIDEV_OFF			0x140#define CR0_JT_CONFIG_OFF			0x3C0#define CR0_FRCSMRCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_FRCSMRCOMP_OFF)#define CR0_DSTRENGTHSEL			(IXP2400_DDR_CNTRL_BASE + CR0_DSTRENGTHSEL_OFF)#define CR0_DDQRCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_DDQRCOMP_OFF)#define CR0_DCTLRCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_DCTLRCOMP_OFF)#define CR0_DRCVRCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_DRCVRCOMP_OFF)#define CR0_DCKERCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_DCKERCOMP_OFF)#define CR0_DCSRCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_DCSRCOMP_OFF)#define CR0_DCKRCOMP				(IXP2400_DDR_CNTRL_BASE + CR0_DCKRCOMP_OFF)#define CR0_DX8X16CKECSCKSEL		(IXP2400_DDR_CNTRL_BASE + CR0_DX8X16CKECSCKSEL_OFF)#define CR0_RCOMPPRD				(IXP2400_DDR_CNTRL_BASE + CR0_RCOMPPRD_OFF)#define CR0_DIGFIL					(IXP2400_DDR_CNTRL_BASE + CR0_DIGFIL_OFF)#define CR0_SLEWPROGRAMMED			(IXP2400_DDR_CNTRL_BASE + CR0_SLEWPROGRAMMED_OFF)#define CR0_OVRRIDEH				(IXP2400_DDR_CNTRL_BASE + CR0_OVRRIDEH_OFF)#define CR0_OVRRIDEV				(IXP2400_DDR_CNTRL_BASE + CR0_OVRRIDEV_OFF)#define CR0_JT_CONFIG				(IXP2400_DDR_CNTRL_BASE + CR0_JT_CONFIG_OFF)/*SDRAM controller register bits*/#define TCL						(1 << 2)#define TRAS					(0 << 4)#define TRC						(1 << 6)#define TWTR					(1 << 10)#define REF_EN					(1 << 14)#define NUM_ROW_COL				(3 << 23)#define NUM_SIDES				(1 << 26)#define TWR						(0 << 27)#define TRRD					(1 << 28)#define	TRFC					(0 << 29)#define REF_COUNT				(11 << 15)#define DU_CONTROL_VAL			(TRRD | NUM_SIDES | NUM_ROW_COL | REF_COUNT | REF_EN | TWTR | TRC | TCL)/*DRAM initialization register bits*/#define CKE					(1 << 16)#define PRECHARGE			(1 << 29)#define REFRESH				(1 << 30)#define LD_MODE_REG			(1 << 31)#define DU_INIT_VAL			(REFRESH | PRECHARGE | CKE)#define RESET_DLL					0x100#define LOAD_MODE_NORMAL			0x62#define PRECHARGE_ALL				(1 << 10)#define EXT_LD_MODE					(1 << 12)#define SIDE0						(1 << 14)#define SIDE1						(1 << 15)#define CKE							(1 << 16)#define DDR_RX_DLL_VAL				0x11#define DDR_RX_DESKEW_VAL			0x11#define DDR_RDDLYSEL_RECEN_VAL		0x11/************//*DRAM ECC test register bits*/#define DISABLE_CHK			(1 << 8)/*--------------------------------------------------- *IXDP2400 MSF CSRs... * -------------------------------------------------- */#define IXP2400_MSF_CSR_BASE 			0xC8000000/*--------------------------------------------------- *IXDP2400 SRAM controller... * -------------------------------------------------- *//* sram registers */#define IXDP2400_SRAM_CSR_BASE			    0xCC000000#define IXDP2400_SRAM_RING_BASE				0xCE000000#define IXP2400_QDR_CH_CSR_BASE				0xCC010000#define IXP2400_QDR_CH_CONTROL_OFF			0x0#define IXP2400_QDR_RX_DLL_OFF				0x228#define IXP2400_QDR_RD_PTR_OFF				0x240#define IXP2400_QDR_RX_DESKEW_OFF			0x244#define IXP2400_QDR_RCMP_SETUP_CONTROL_OFF	0x300#define IXP2400_QDR_RCOMP_OFF				0x318 #define IXP2400_SRAM_CH0_BASE		    	0x80000000#define IXP2400_SRAM_CH1_BASE		    	0x90000000#define IXDP2400_SRAM_CH0_BIT_SET_OPS_BASE	0x84000000#define IXDP2400_SRAM_CH0_BIT_CLR_OPS_BASE	0x88000000#define IXDP2400_SRAM_CH0_ADD_OPS_BASE		0x8C000000#define IXDP2400_SRAM_CH1_BIT_SET_OPS_BASE	0x94000000#define IXDP2400_SRAM_CH1_BIT_CLR_OPS_BASE	0x98000000#define IXDP2400_SRAM_CH1_ADD_OPS_BASE		0x9C000000#define SRAM_200MHZ_DIVISOR			0x3#define SRAM_150MHZ_DIVISOR			0x4#define SDRAM_DIVISOR			    0x4#define PIPELINE					(1 << 10)#define PARITY_ENABLE			    (1 << 3)#define MIN_SRAM_SIZE			    (1024 * 1024) /* 1MB SRAM */#define MAX_SRAM_SIZE			    (32 * 1024 * 1024) /* 32MB SRAM */#define MAX_SRAM_SIZE_CSR_VAL	    (0xA << 7)#define SRAM_SIZE_LOOPS			    4#define MAX_QDR_CHANNEL				2#define QDR_DLL_FREQ_SEL 0x3#define QDR_DLL_TAP_SEL 0x2#define QDR_RD_PTR		0x1/* Define macros for fixing 8 and 16 bit addresses for big-endian operation */#if (_BYTE_ORDER == _BIG_ENDIAN)#define FIX_ADDR_16(x) ((x) ^ 2)#define FIX_ADDR_32(x) ((x) ^ 3)#else#define FIX_ADDR_16(x) (x)#define FIX_ADDR_32(x) (x)#endif/*--------------------------------------------------- *IXDP2400 PCI unit... *--------------------------------------------------- */#define CSR_BAR                 0#define SRAM_BAR                1#define SD_BAR                  2#define NO_BAR                  3#define IXP2400_VENDOR_ID		0x8086#define IXP2400_DEVICE_ID		0x9001#define PCI_CONFIG1_BASE        0xDB000000 /* Config cycle 1 space */#define PCI_CONFIG0_BASE        0xDA000000 /* Config cycle 0 space */#define PCI_IO_BASE             0xD8000000 /* I/O cycle space */#define PCI_MEM_BASE            0xE0000000 /* Mem cycle space */#define INIT_COMP				(1 << 21)#define RESET_DRAM0				(1 << 11)#define RESET_SRAM1				(1 << 4)#define RESET_SRAM0				(1 << 3)#define PCIRST					(1 << 2)#define RESET_PCI				(1 << 1)
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