📄 ixdp2400.h
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/* ixdp2400.h - header for ixdp2400 eval board *//* Copyright 2001 Wind River Systems, Inc. *//*modification history--------------------01b,15jan03,scm correct var declarations to support serial only mode...01a,29mar02,vgd written from brh80200.h, version 01a*//*DESCRIPTIONThis file contains I/O address and related constants for theIXDP2400 platform*/#ifndef INCIXDP2400h#define INCIXDP2400h#ifdef __cplusplusextern "C" {#endif/*IXP VERSION for IXDP2400*/#define IXP_VERSION "1.01.001" /* format "major.minor.build" *//*--------------------------------------------------- * Defintion for Bit macro * --------------------------------------------------*/#ifndef BIT#define BIT(bitNumber) (1 << (bitNumber))#endif /* BIT *//*--------------------------------------------------- *IXP2400 Register access Macros * --------------------------------------------------*/#define IXP2400_REG_READ(reg,result) \ ((result) = *(volatile UINT32 *)(reg))#define IXP2400_REG_WRITE(reg,data) \ (*((volatile UINT32 *)(reg)) = (data))/*--------------------------------------------------- * IXDP2400 Constants... * --------------------------------------------------*/#define SZ_0 0x00000000#define SZ_1 0x00000001#define SZ_2 0x00000002#define SZ_4 0x00000004#define SZ_8 0x00000008#define SZ_16 0x00000010#define SZ_32 0x00000020#define SZ_48 0x00000030#define SZ_64 0x00000040#define SZ_128 0x00000080#define SZ_256 0x00000100#define SZ_512 0x00000200#define SZ_1K 0x00000400#define SZ_2K 0x00000800#define SZ_4K 0x00001000#define SZ_8K 0x00002000#define SZ_16K 0x00004000#define SZ_32K 0x00008000#define SZ_64K 0x00010000#define SZ_128K 0x00020000#define SZ_256K 0x00040000#define SZ_512K 0x00080000#define SZ_1M 0x00100000#define SZ_2M 0x00200000#define SZ_3M 0x00300000#define SZ_4M 0x00400000#define SZ_8M 0x00800000#define SZ_16M 0x01000000#define SZ_32M 0x02000000#define SZ_48M 0x03000000#define SZ_64M 0x04000000#define SZ_128M 0x08000000#define SZ_224M 0x0e000000 #define SZ_256M 0x10000000#define SZ_480M 0x1e000000#define SZ_512M 0x20000000#define SZ_1G 0x40000000#define SZ_2G 0x80000000/*--------------------------------------------------- * IXDP2400 global registers *--------------------------------------------------- */#define IXP2400_CAP_BASE 0xC0000000#define IXP2400_GLOBAL_CNTRL (IXP2400_CAP_BASE + 0x4A00)#define IXP2400_PROD_ID (IXP2400_GLOBAL_CNTRL + 0x00)#define IXP2400_MISC_CONTROL (IXP2400_GLOBAL_CNTRL + 0x04)#define IXP2400_MSF_ClK_CNTRL (IXP2400_GLOBAL_CNTRL + 0x08)#define IXP2400_RESET_1 (IXP2400_GLOBAL_CNTRL + 0x10) #define IXP2400_RESET_0 (IXP2400_GLOBAL_CNTRL + 0x0C) #define IXP2400_CLOCK_CONTROL (IXP2400_GLOBAL_CNTRL + 0x14) #define IXP2400_STRAP_OPTIONS (IXP2400_GLOBAL_CNTRL + 0x18)/*IXP2400_STRAP_OPTIONS register bits*/#define CFG_PCI_BOOT_HOST BIT(2) #define CFG_PROM_BOOT BIT(1) #define NO_BOOT_ROM 0x0/*IXP2400_PROD_ID register bits*/#define MAJ_PROD_TYPE 0x001F0000#define MIN_PROD_TYPE 0x0000FF00 #define MAJ_REV 0x000000F0 #define MIN_REV 0x0000000F#define PROD_ID 0xFFFFFFFF/* IXP2400_MISC_CONTROL register bits*/#define FLASH_WRITE_ENABLE BIT(9) #define FLASH_ALIAS_DISABLE BIT(8)/*--------------------------------------------------- * IXDP2400 GPIO... * --------------------------------------------------*/#define IXP2400_GPIO_BASE (IXP2400_CAP_BASE + 0x10000)/*Read only register to read the level/data on the pins irrespective of input or output*/#define IXP2400_GPIO_PLR (IXP2400_GPIO_BASE + 0x0) /*write a one to this register's bit to configure the corressponding pin as output*/#define IXP2400_GPIO_PDSR (IXP2400_GPIO_BASE + 0x08)#define IXP2400_GPIO_POPR (IXP2400_GPIO_BASE + 0x10) /*write a one to this register's bit to configure corressponding bit as input*/#define IXP2400_GPIO_PDCR (IXP2400_GPIO_BASE + 0x0c)/*write to this register's bit to set data high*/#define IXP2400_GPIO_POSR (IXP2400_GPIO_BASE + 0x14)/*write to this register's bit to set data low*/ #define IXP2400_GPIO_POCR (IXP2400_GPIO_BASE + 0x18) /*------------------------------------------------------ * IXDP2400 Scratch .......... *------------------------------------------------------*/#define IXP2400_SCRATCH_BASE 0xCA000000#define IXP2400_SCRATCH_CSR_BASE 0xC0004800#define VXWORKS_TEXT_ADDR_LOC 0xCA000100#ifndef _ASMLANGUAGEextern UINT32 ixp2400XtalFreq;#endif#define IXP2400_DEFAULT_CLK_RATE 600000000 /*600 MHz*//*--------------------------------------------------- * IXDP2400 UART... * --------------------------------------------------*/#define IXP2400_UART_XTAL ixp2400XtalFreq#define CPU_SPEED_600MHZ/* UART base address */#define IXP2400_UART_ADDR IXP2400_CAP_BASE+0x30000/* Byte space between registers */#define IXP2400_UART_REG_DELTA 1 /* only one uart per NPU */#define IXP2400_UART_N_UARTS 1/* *----------------------------------------------------------- * IXP2400 SLOWPORT CSRs... *----------------------------------------------------------- */#define IXP2400_SP_CSR_BASE IXP2400_CAP_BASE + 0x80000#define SP_CCR_OFF 0x0#define SP_WTC1_OFF 0x4#define SP_WTC2_OFF 0x8#define SP_RTC1_OFF 0xC#define SP_RTC2_OFF 0x10#define SP_PCR_OFF 0x18#define SP_ADC_OFF 0x1c#define SP_FAC_OFF 0x20#define SP_FRM_OFF 0x24#define IXP2400_SP_CCR (IXP2400_SP_CSR_BASE + SP_CCR_OFF)#define IXP2400_SP_WTC1 (IXP2400_SP_CSR_BASE + SP_WTC1_OFF)#define IXP2400_SP_WTC2 (IXP2400_SP_CSR_BASE + SP_WTC2_OFF)#define IXP2400_SP_RTC1 (IXP2400_SP_CSR_BASE + SP_RTC1_OFF)#define IXP2400_SP_RTC2 (IXP2400_SP_CSR_BASE + SP_RTC2_OFF)#define IXP2400_SP_PCR (IXP2400_SP_CSR_BASE + SP_PCR_OFF)#define IXP2400_SP_ADC (IXP2400_SP_CSR_BASE + SP_ADC_OFF)#define IXP2400_SP_FAC (IXP2400_SP_CSR_BASE + SP_FAC_OFF)#define IXP2400_SP_FRM (IXP2400_SP_CSR_BASE + SP_FRM_OFF)#define DIVIDE_BY_1 0x0#define DIVIDE_BY_30 0x24#define USE_32_BIT 0x3#define USE_8_BIT_DATA 0x1#define USE_32_BIT_DATA 0x0#define WR_HD 0x1#define WR_PW 0x2#define WR_SU 0x0#define RD_HD 0x1#define RD_PW 0x2#define RD_SU 0x3#define SP_WTC1_VAL (WR_SU << 6 | WR_PW << 2 | WR_HD)#define SP_RTC1_VAL (RD_SU << 6 | RD_PW << 2 | RD_HD)/* I2C defines */#define ADUC812_DEV_ID 0x8C#define TEMP_DEV_ID 0x31/* *------------------------------------------------------ *CPLD registers *------------------------------------------------------ */#define IXP2400_SLOW_PORT_BASE 0xC4000000#define CPLD_CSR_BASE (IXP2400_SLOW_PORT_BASE + 0x3000000)#define SYSTEM_LED_REG_OFF 0x0#define ALPHANUM_DIS_DATA_OFF 0x4#define CPLD_INT_OFF 0xC#define CPLD_REV_OFF 0x10#define SYS_CLK_M_OFF 0x14#define SYS_CLK_N_OFF 0x18#define CPLD_INTMASK_OFF 0x48#define SYSTEM_LED (CPLD_CSR_BASE + SYSTEM_LED_REG_OFF)#define ALPHANUM_DIS_DATA (CPLD_CSR_BASE + ALPHANUM_DIS_DATA_OFF)#define CPLD_INT (CPLD_CSR_BASE + CPLD_INT_OFF)#define CPLD_REV (CPLD_CSR_BASE + CPLD_REV_OFF)#define SYS_CLK_M (CPLD_CSR_BASE + SYS_CLK_M_OFF)#define SYS_CLK_N (CPLD_CSR_BASE + SYS_CLK_N_OFF)#define CPLD_INTMASK (CPLD_CSR_BASE + CPLD_INTMASK_OFF)/* CPLD interrupt bits */#define SLAVE_NPU_INT (1 << 0)#define ADUC812_INT (1 << 7)#define MEDIA_SLOWPORT_BASE (IXP2400_SLOW_PORT_BASE + 0x2000000)#define MSF_SLOWPORT_BASE (IXP2400_SLOW_PORT_BASE + 0x2800000) /* *-------------------------------------------------------- *IXDP2400 4 char Display/LCD Encodings *-------------------------------------------------------- */#define DISPLAY_NULL (0x20)#define DISPLAY_0 (0x30)#define DISPLAY_1 (0x31)#define DISPLAY_2 (0x32)#define DISPLAY_3 (0x33)#define DISPLAY_4 (0x34)#define DISPLAY_5 (0x35)#define DISPLAY_6 (0x36)#define DISPLAY_7 (0x37)#define DISPLAY_8 (0x38)#define DISPLAY_9 (0x39)#define DISPLAY_A (0x41)#define DISPLAY_B (0x42)#define DISPLAY_C (0x43)#define DISPLAY_D (0x44)#define DISPLAY_E (0x45)#define DISPLAY_F (0x46)#define DISPLAY_G (0x47)#define DISPLAY_H (0x48)#define DISPLAY_I (0x49)#define DISPLAY_J (0x4A)#define DISPLAY_K (0x4B)#define DISPLAY_L (0x4C)#define DISPLAY_M (0x4D)#define DISPLAY_N (0x4E)#define DISPLAY_O (0x4F)#define DISPLAY_P (0x50)#define DISPLAY_Q (0x51)#define DISPLAY_R (0x52)#define DISPLAY_S (0x53)#define DISPLAY_T (0x54)#define DISPLAY_U (0x55)#define DISPLAY_V (0x56)#define DISPLAY_W (0x57)#define DISPLAY_X (0x58)#define DISPLAY_Y (0x59)#define DISPLAY_Z (0x5A)#define DIGIT_0 (0x0)#define DIGIT_1 (0x1)#define DIGIT_2 (0x2)#define DIGIT_3 (0x3)#define WRITE_TO_CHAR_RAM (0x48)#define DISPLAY_ASCII (0x18)/*--------------------------------------------------------------- * IXDP2400 timer................ *--------------------------------------------------------------- */#define IXP2400_TIMER_BASE (IXP2400_CAP_BASE + 0x20000)/*Timer Control Register offsets*/#define T1_CTL 0x00 #define T2_CTL 0x04#define T3_CTL 0x08⌨️ 快捷键说明
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