rominit.s

ixp2400 bsp for vxworks

	ldr r0, =CR0_OVRRIDEH	
	str	r1, [r0]

/* cr0_ovrridev: turn off v override, 0x0 */
	ldr r0, =CR0_OVRRIDEV
	str	r1, [r0]

/* De-Select Test Mode (cr0_jt_config) at address offset 0x3C0 
 * User Overide RCOMP settings 
 */
	ldr r0, =CR0_JT_CONFIG
	str	r1, [r0]


/* wait for 4000 cycles*/
		mov r0, #0x0
wait_ddr_io:
		add r0, r0, #1
		cmp r0, #2000
		bne wait_ddr_io

		HEX_DISPLAY_THIS(r0, r1, DISPLAY_D, DISPLAY_D, DISPLAY_R, DISPLAY_1)


	/* now config SDRAM interface*/
		ldr	r0, =IXP2400_DU_CONTROL		/* Load the address of the dram controller control Register in r0*/
		ldr	r1, =DU_CONTROL_VAL			/* Load value in r1*/
		str	r1, [r0]					/* Store to dram controller control Register*/

	/* enable clock*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =CKE
		str	r1, [r0]

	/* precharge all*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =(PRECHARGE | SIDE1 | SIDE0 | PRECHARGE_ALL)
		str	r1, [r0]

wait_precharge1:
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #PRECHARGE
		bne wait_precharge1

	/* issue EMRS to enable DLL*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =(LD_MODE_REG | SIDE1 | SIDE0 | EXT_LD_MODE)
		str	r1, [r0]

wait_enable:
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #LD_MODE_REG
		bne wait_enable

	/* Reset DLL*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =(LD_MODE_REG | SIDE1 | SIDE0 | RESET_DLL)
		str	r1, [r0]

wait_reset:
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #LD_MODE_REG
		bne wait_reset

	/* precharge all*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =(PRECHARGE | SIDE1 | SIDE0 | PRECHARGE_ALL)
		str	r1, [r0]

wait_precharge2:
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #PRECHARGE
		bne wait_precharge2

	/* issue 2 auto refresh commands*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =(REFRESH | SIDE1 | SIDE0)
		str	r1, [r0]

wait_refresh1:
	/* wait till auto refresh is done*/
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #REFRESH
		bne wait_refresh1

		ldr	r0, =IXP2400_DU_INIT 
		ldr	r1, =(REFRESH | SIDE1 | SIDE0)
		str	r1, [r0]

wait_refresh2:
	/* wait till auto refresh is done*/
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #REFRESH
		bne wait_refresh2

	/* init device operation*/
	/* settings - burst length = 4, burst type - sequential, CAS latency = 2*/
		ldr	r0, =IXP2400_DU_INIT
		ldr	r1, =(LD_MODE_REG | SIDE1 | SIDE0 | LOAD_MODE_NORMAL)
		str	r1, [r0]

wait_start:
		ldr r0, =IXP2400_DU_INIT
		ldr r1, [r0]
		tst	r1, #LD_MODE_REG
		bne wait_start

		HEX_DISPLAY_THIS(r0, r1, DISPLAY_D, DISPLAY_D, DISPLAY_R, DISPLAY_NULL)
	
	/* disable ecc so that it doesn't generate ecc errors.*/
	/* even if you disable ecc ecc will be calculated and stored*/
		ldr r0, =IXP2400_DU_ECC_TEST	/* load the register address in r0*/        
    	ldr r1, [r0]					/* read the reg contnets into r1*/
    	orr r1, r1, #DISABLE_CHK		/* set the disable bit*/
    	str r1, [r0]					/* write the value to the register*/


		/* Scrubbing Memory */
        ldr     r11, =IXP2400_SDRAM_BASE_ADDR  	/* base address of SDRAM */
        ldr     r12, =SZ_512M                   /* size of the memory to scrub 256 MB */ /*ixp2400 */
       

        mov     r0, #0x00000000
        mov     r1, #0x00000000
        mov     r2, #0x00000000
        mov     r3, #0x00000000
        mov     r4, #0x00000000
        mov     r5, #0x00000000
        mov     r6, #0x00000000
        mov     r7, #0x00000000

		/* disable ecc check before scrubing DRAM so that it doesn't 
		 * generate ecc errors.even if you disable ecc chk ecc will be 
		 * calculated and stored
     	 */
		ldr r0, =IXP2400_DU_ECC_TEST 		/* load the register address in r0*/       
    	ldr r1, [r0]						/* read the reg contnets into r1*/
    	orr r1, r1, #DISABLE_CHK			/* set the disable bit*/
    	str r1, [r0]						/* write the value to the register*/


10: 	/*ScrubNext32Bytes:*/
        stmia   r11!, {r0-r7}           	/* Write 64-bit wide data */
        subs    r12, r12, #0x00000020
        bne     10b 						/*ScrubNext32Bytes*//* Write Next 32 bytes */

12: 	/*ScrubDone:*/
		/*enable ECC_chk again*/    
		ldr r0, =IXP2400_DU_ECC_TEST		/* Load the register addr into r0*/
    	ldr r1, [r0]			    		/* load the register contents into r1*/
    	bic r1, r1, #DISABLE_CHK			/* clear the DISABLE_CHK bit*/
    	str r1, [r0]						/* write it back to the register*/
	

		HEX_DISPLAY_THIS(r0, r1, DISPLAY_S, DISPLAY_C, DISPLAY_R, DISPLAY_B)

				
		b mmu_setup
		
	

warm_start:
		
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_W, DISPLAY_A, DISPLAY_R, DISPLAY_M)

		/* Disable Interrupts */
        MRS     r1, cpsr                /* get current status */
        ORR     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */
        MSR     cpsr, r1

		/* Interrupts Disabled */
        ldr     r0, =IXP2400_IRQ_ENABLE_CLR_REG /* Mask Interrupts */
        ldr     r2, =IXP2400_MASK_ALL_INT
        str     r2, [r0]

		/*First disable MMU in case of coming from BM or if startType is WARM,
		 * because BM must have enabled the MMU
		 */
		/* Disable MMU */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register */
        bic     r0, r0, #1              /* diab does not handle >>>"and r0, r0, #0xfffffffe" */ /* disable MMU */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Register */
        CPWAIT  (r0)                    /* Wait */


mmu_setup:
				/*** MMU Setup ***/


		/* Enable access to all coprocessor registers*/
		ldr	r0, =0x2001			
		mcr	p15, 0, r0, c15, c1, 0


		/*** Disable Write Buffer Coalescing ***/

	   	mcr     p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
    	CPWAIT  (r0)                      /* wait for the write to happen */
    	
	/* Invalidate I-Cache, D-Cache, and BTB */
        mcr     p15, 0, r0, c7, c7, 0
        CPWAIT  (r0)                      /* Wait */
	
	/* Invalidate Instruction, Data TLBs */
        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/
        CPWAIT  (r0)                      /* Wait */
	
	/* Enable Instruction Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register*/
        orr     r0, r0, #0x1000         /* Set I-Cache bit */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back Control Register */
        CPWAIT  (r0)                      /* Wait */
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_I, DISPLAY_C, DISPLAY_A, DISPLAY_C)

				
		cmp r10, #CFG_PROM_BOOT         /*if not running out of flash, the mmu table is in RAM*/
		bne RAM_TTBASE 
		
		tst r8, #BOOTROM_THRU_BM		/*if it is Bootrom thru BM, is at a flash offset*/
		bne BootRom_TTBase	

		tst r8, #BOOT_THRU_BM			/*if it is vxworks_rom thru BM, the mmu table is in RAM*/
		bne RAM_TTBASE	
		
	/* Set Translation Table Base */ 
	    ldr     r0, =ROM_MMU_TABLE_ADR 
        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */
        CPWAIT  (r0)                      /* Wait */
		b BootRom_TTBase_Done

BootRom_TTBase:
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_B, DISPLAY_R, DISPLAY_D, DISPLAY_1)
		/* Set Translation Table Base */ 
		ldr r1, =VXWORKS_TEXT_ADDR_LOC
		ldr r0, [r1]
		sub r0,r0,#0x4000
	    mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */
        CPWAIT  (r0)                      /* Wait */

BootRom_TTBase_Done:

		/* Set Domain Access Control Register */
		ldr     r0, =0x55555555         /* Set All 16 domains to manager access */
		mcr     p15, 0, r0, c3, c0, 0   /* Set Domain Permissions */ 
        CPWAIT  (r0)                      /* Wait */
		
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_T, DISPLAY_T, DISPLAY_B, DISPLAY_1)

		/* Enable MMU */
       	mrc	p15, 0, r0, c1, c0, 0
		orr	r0, r0, #MMU_Control_M
		orr	r0, r0, #MMU_Control_R
		mcr	p15, 0, r0, c1, c0, 0
		CPWAIT  (r0)


		b copy_end

		


RAM_TTBASE:	
		
	/* 
	 * Copy two instructions from ROM to SDRAM, starting at
	 * copy_start 
	 */

		ADR	r1, copy_start
		LDMIA	r1, {r2-r4}
	
	/*
	 * The following two instructions implements:
	 * ADD	r1, r1, #SDRAM_VIRT_OFFSET
	 * but it must be broken into two instructions because otherwise

	 * ADD	r1, r1, #(SDRAM_VIRT_OFFSET & 0xff000000)
     * ADD	r1, r1, #(SDRAM_VIRT_OFFSET & 0x00ff0000)
	 * the constant is too big
	 */

		sub r1,r1, #(0x02000000)
		
		STMIA	r1, {r2-r4}
		
#if SINGLE_BOOTROM

		ldr     r0, =0x4000             /*SLAVE_RAM_MMU_TABLE_ADDR*/
       	mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */
       	CPWAIT  (r0)                      /* Wait */
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_T, DISPLAY_T, DISPLAY_B, DISPLAY_3)
#else	

	   	ldr     r0, =(SDRAM_HIGH_PHY + mmu_table) 
        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */
        CPWAIT  (r0)                      /* Wait */
		
#endif

		/* Set Domain Access Control Register */
		ldr     r0, =0x55555555         /* Set All 16 domains to manager access */
		mcr     p15, 0, r0, c3, c0, 0   /* Set Domain Permissions */ 
        CPWAIT  (r0)                      /* Wait */
	

		HEX_DISPLAY_THIS(r0, r1, DISPLAY_T, DISPLAY_T, DISPLAY_B, DISPLAY_2)

enable_mmu:

		/* Enable MMU */
       	mrc	p15, 0, r0, c1, c0, 0
		orr	r0, r0, #MMU_Control_M
		orr	r0, r0, #MMU_Control_R
		mcr	p15, 0, r0, c1, c0, 0
		
		
copy_start:

		mov r6, #SDRAM_HIGH_PHY		
		sub r6, PC, r6
		mov	PC, r6 							/*jump to phy hi sdram */



	
copy_end:
	
        
        HEX_DISPLAY_THIS(r0, r1, DISPLAY_M, DISPLAY_M, DISPLAY_U, DISPLAY_NULL)
		
	
		/*** Data Cache Setup ***/

		/* Drain Write/Fill Buffers */
		mcr     p15, 0, r0, c7, c10, 4  /* Drain */
        CPWAIT  (r0)                      /* Wait */

		/* Enable Data Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000004     /* Enable Data Cache */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back */
        CPWAIT  (r0)                      /* Wait */

	
	 /* Initialize branch target buffer*/
    mrc     p15, 0, r0, c1, c0, 0
    orr     r0, r0, #MMU_Control_BTB
    mcr     p15, 0, r0, c1, c0, 0
    CPWAIT  (r0)

        HEX_DISPLAY_THIS(r0, r1, DISPLAY_C, DISPLAY_A, DISPLAY_C, DISPLAY_H)
     

/******************************************************************************/
vxWorks_boot:
      
		ldr r1, =_vectorTable
		
		cmp r1, #RAM_HIGH_ADRS
		bne 111f
		orr r8, r8, #BOOT_CMP_IMAGE	

111:
		/*  Now jump to the code that starts the whole vxWorks boot process */
        mov     r0, r8
        ldr     sp, L$STACK_ADDR

		
		cmp r10, #CFG_PROM_BOOT        
		bne 10f 
		tst r8, #BOOT_THRU_BM
		bne 10f
    	 
		ldr     pc, L$StrtInRom 

10: 	 

		tst r8, #BOOTROM_THRU_BM
		beq 20f
		
		ldr		pc, L$StrtInRom1

20:
		ldr     pc, L$StrtInRam
     
/******************************************************************************/     
		
L$StrtInRom:    .long   ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
L$STACK_ADDR:   .long   STACK_ADRS
L$StrtInRam:    .long   FUNC(romStart)
L$StrtInRom1:   .long   BOOTROM_OFFSET + FUNC(romStart) - RAM_LOW_ADRS