rominit.s

ixp2400 bsp for vxworks

		str r1,[r2]
	
		/* The Boot Monitors stores the flash offset at which vxworks_rom 
		 * resides in Mail box1 and the flash offset where bootrom resides 
         * in Mailbox2. If mailbox1 contains a flash address, then the image 
         * is Vxworks_rom. otherwise the image is bootrom and the flash offset
         * for bootrom will be Mailbox 2.Accordingly set the BOOTROM_THRU_BM
		 * flag
         */

		and r1, r1, #IXP2400_FLASH_BASE
		cmp r1, #IXP2400_FLASH_BASE
		beq 100f
		ldr r2, =IXP2400_MAILBOX2
		ldr r1, [r2]
		and r1, r1, #IXP2400_FLASH_BASE
		cmp r1, #IXP2400_FLASH_BASE
		bne 100f
		ldr r2, =IXP2400_MAILBOX2
		ldr r1, [r2]
		ldr r2, =VXWORKS_TEXT_ADDR_LOC 
		str r1,[r2]
		orr r0,r0,#BOOTROM_THRU_BM
		

		

100:   		MOV     r8, r0           /* store off startType */


#if (_BYTE_ORDER == _BIG_ENDIAN)
	  /* switch to big endian mode first thing so that we don't have to mess with constants*/
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x80           /* set bit7, enable big endian */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Control Reg */
#endif 

	
		ldr r0,  =IXP2400_STRAP_OPTIONS	/* Load the address of the strap options Register in r0*/
		ldr r1,  [r0]				    /* get value in r1*/
		and r9,  r1, #CFG_PCI_BOOT_HOST	/* save master/slave id in r9*/
		and r10, r1, #CFG_PROM_BOOT		/* save single/dual boot rom in r10*/

		tst     r8, #BOOT_THRU_BM 		/*if booting thru BM, jump*/
    	bne     SP_CFG
		
		/* fall through to warm boot entry
    	cmp     r8, #BOOT_COLD
    	bne     warm_start*/
   	
		/*configure Slowport*/

		/*The work around for sausolito bUg #1199 is to set teh clock doivisor
		 *in SP_CCR to 1. as the default is 1:1 no change needed in our code
		 */

		/* read the value of SP_RTC and put it in WTC register*/
SP_CFG:
		ldr r0, =IXP2400_SP_RTC1
		ldr r1, [r0]
		ldr	r0, =IXP2400_SP_WTC1 /* Load the address of the slow port write timing control Register in r0*/
		str	r1, [r0]			 /* Store to slow port write timing control Register*/

		ldr	r0, =IXP2400_SP_WTC2 /* Load the address of the slow port write timing control Register in r0*/
		str	r1, [r0]			 /* Store to slow port write timing control Register*/

		ldr	r0, =IXP2400_SP_RTC2 /* Load the address of the slow port write timing control Register in r0*/
		str	r1, [r0]			 /* Store to slow port write timing control Register*/

		ldr	r0, =IXP2400_MISC_CONTROL		/* Load the address of the misc control Register in r0*/
		ldr	r1, [r0]						/* store old value in r1*/
		ldr r2, =FLASH_WRITE_ENABLE
		orr r1, r1, r2						/* make flash write enable for flash utility*/
		str	r1, [r0]						/* Store to misc control Register*/


		HEX_DISPLAY_THIS(r0, r1, DISPLAY_S, DISPLAY_P, DISPLAY_D, DISPLAY_N)

		
		cmp r10, #CFG_PROM_BOOT   /*if not running out of flash, we need not do unaliasing of flash*/
		bne mmu_setup 
		
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_P, DISPLAY_C, DISPLAY_I, DISPLAY_R)

		cmp r9, #CFG_PCI_BOOT_HOST /*if not master NPU jump*/
		bne pci_reset_out

		ldr	r0, =IXP2400_RESET_0
		ldr	r1, [r0]
		orr	r1, r1, #PCIRST
		orr	r1, r1, #RESET_PCI
		str	r1, [r0]
		ldr	r3, =0x0
pci_reset_loop:
		add r3, r3, #1
		cmp r3, #200
		bne pci_reset_loop

pci_reset_out:
		/* take pci out of reset*/
		ldr	r0, =IXP2400_RESET_0
		ldr	r1, [r0]
		bic	r1, r1, #PCIRST
		bic	r1, r1, #RESET_PCI
		str	r1, [r0]
	
		/* 8 dummy writes to flush pci cmd fifo*/
pci_cmd_fifo_flush:
		mov r3, #0x0
		ldr	r0, =IXP2400_MAILBOX0
		ldr	r1, =0x0
pci_cmd_fifo_flush_loop:
		str	r1, [r0]
		add r3, r3, #1
		cmp r3, #8
		bne pci_cmd_fifo_flush_loop

#if A0_REV
		/* set PCI rcomp registers*/
		ldr	r0, =IXP2400_PCI_RCOMP_OVER
		ldr	r1, =0x153239
		str	r1, [r0]

		/* set slave's pci rcomp register within 2000 cycles. */
		ldr	r0, =0xDA200060
		ldr	r1, =0x153239
		str	r1, [r0]
#endif

		cmp     r8, #BOOT_COLD
    	bne     warm_start

		cmp r9, #CFG_PCI_BOOT_HOST 
		bne flash_unalias

		HEX_DISPLAY_THIS(r0, r1, DISPLAY_U, DISPLAY_N, DISPLAY_A, DISPLAY_L)

flash_unalias:		
		tst r8, #BOOT_THRU_BM
		bne warm_start

		/*if not running out of flash, we need not do unaliasing of flash*/
		cmp r10, #CFG_PROM_BOOT         
		bne warm_start 	

		/*load the registers with everything that is needed for unalising the flash*/

		ldr	r0, =IXP2400_MISC_CONTROL	/* Load the address of the misc control Register in r0*/
		ldr	r1, [r0]					/* store old value in r1*/
		ldr r2, =FLASH_ALIAS_DISABLE
		orr r1, r1, r2					/* disable flash aliasing bit*/

		/*jump to real flash address before you unalias flash
	 	 *we cannot use a b instruction as b allows jumps only with 32MB.
 	 	 *the alternative is to load the PC directly with the address 
  	 	 *where we want to jump 
	 	 */ 
		ldr r2, =IXP2400_FLASH_BASE
		add r2, r2, PC
		mov	PC, r2 						/*jump to real flash address */
		str	r1, [r0]					/*Store to misc control Register to unalias flash*/
		
		HEX_DISPLAY_THIS(r0, r1, DISPLAY_R, DISPLAY_E, DISPLAY_A, DISPLAY_L)

ddr_rcomp:
		/* now set DRAM rcomp IO config registers*/
		ldr	r0, =DDR_RCOMP_IO_CONFIG
		ldr	r1, =DDR_RCOMP_IO_CONFIG_VAL
		str	r1, [r0]

clock_setup:

#if A0_REV

		ldr r0, =SYS_CLK_M
		ldr r1, [r0]
		and r1, r1, #0xFF
		ldr r4, =SRAM_150MHZ_DIVISOR
		cmp r1, #0x55
		bne sram_divisor_set
#endif
		ldr r4, =SRAM_200MHZ_DIVISOR


sram_divisor_set:
		/* now set the operating freq. for SRAM/SDRAM interface */
		ldr	r0, =IXP2400_CLOCK_CONTROL		/* Load the address of the clock control Register in r0 */
		ldr	r1, [r0]						/* store old value in r1 */
		ldr r2, =(~(0xF00FF))
		and r1, r1, r2						/* clear sdram and sram divisor default value */
		orr r1, r1, #(SDRAM_DIVISOR << 16)	/* Set SDRAM clock ratio */
		mov r5, r4, lsl #4
		orr r1, r1, r5						/* Set SRAM channel 1 clock ratio */
		orr r1, r1, r4						/* Set SRAM channel 0 clock ratio */
		mov r3, #0x0
		mcr p15, 0, r0, c7, c10, 4    		/* DCU drain instruction */
		b clk_stab

		/* wait for some time so that clock gets stabilized
		 * make this code aligned at 32 bytes so that it is 
		 * aligned on prefatch boundary 
         */
		.p2align 5

clk_stab:
		str	r1, [r0]						/* Store to clock control Register */
clk_stab_loop:
		add r3, r3, #1
		cmp r3, #0x200
		bne clk_stab_loop
		b clk_stab_done

		.p2align 5

clk_stab_done:
		
		/*set the DRAM I/O CSRs*/
				
		ldr	r0, =IXP2400_DDR_RDDLYSEL_RECEN
		ldr	r1, =DDR_RDDLYSEL_RECEN_VAL
		str	r1, [r0]

		ldr	r0, =IXP2400_DDR_RX_DLL
		ldr	r1, =DDR_RX_DLL_VAL
		str	r1, [r0]

		ldr	r0, =IXP2400_DDR_RX_DESKEW
		ldr	r1, =DDR_RX_DESKEW_VAL
		str	r1, [r0]


      /*Rcomp Initialisation, Select Stength for Pin Groups */
	  ldr r0, =CR0_DSTRENGTHSEL
	  ldr r1, =0x036db6db		/* rcv 1.5x rest 1.5x */
	 str	r1, [r0]

	/* Program Rcomp offset registers to 0 (until characterised values are available)
	 * Bit[15] = Sign for pulldown
	 * Bit[14:8] = Value for Pulldown
	 * Bit[7] = Sign for pullup
	 * Bit[6:0] = Value for Pullup 
     */

	   ldr r1, =0x00000000 	
	
	   ldr r0, =CR0_DDQRCOMP		/* DQ/DQS offset*/
	   str	r1, [r0]

 	   ldr	r0, =CR0_DCTLRCOMP		/* MA/BA/RAS#/CAS#/WE# offset*/
	   str	r1, [r0]

	   ldr r0, =CR0_DRCVRCOMP		/* RCV offset*/
	   str	r1, [r0]

	   ldr r0, =CR0_DCKERCOMP		/* CKE offset*/
	   str	r1, [r0]

	   ldr r0, =CR0_DCSRCOMP		/* CS# offset*/
	   str	r1, [r0]

	   ldr r0, =CR0_DCKRCOMP		/* CK/CK# offset [31:16 for X16, 15:0 for x8]*/
	   str	r1, [r0]

	/* Select x8 or x16 slew compensation for CKE, CS, CK */
       ldr r0, =CR0_DX8X16CKECSCKSEL
	   ldr r1, =0x11111111		/* for x8 slew compensation*/
	   str	r1, [r0]

	/* Select rcomp Period */
	   ldr r0, =CR0_RCOMPPRD
	   ldr r1, =0x00000000		/* for period = 2097152 clock cyles*/
	   str	r1, [r0]

	/* set Dig Filter Clamp */
	   ldr r0, =CR0_DIGFIL
	   ldr r1, =0x00000000		/* for no filter*/
	   str	r1, [r0]


	/* Program DDR DQ/DQS pull-up and pull-down Slew Lookup table registers 
	 * (cr0_ddqpslew0 - cr0_ddqpslew3) and (cr0_ddqnslew0 - cr0_ddqnslew3) 
     */

	  ldr r1, =0xcccccccc

	  ldr r0, =0xd0000150
	  ldr r2, =0xd0000188
DQ_DQS:
	  str	r1, [r0]
	  add r0, r0, #0x8
	  cmp r0, r2
	  ble DQ_DQS

	/* Program MA/BA/RAS#/CAS#/WE# pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dctlpslew0 - cr0_dctlpslew3) and (cr0_dctlnslew0 - cr0_dctlnslew3) 
     */
	  ldr r0, =0xd0000198
	  ldr r2, =0xd00001D0
MA_BA_RAS_CAS_WE:
	 str	r1, [r0]
	 add r0, r0, #0x8
	 cmp r0, r2
	 ble MA_BA_RAS_CAS_WE


	/* Program RCV pull-up and pull-down Slew Lookup table registers 
	 * (cr0_drcvpslew0 - cr0_drcvpslew3) and (cr0_drcvnslew0 - cr0_drcvnslew3) 
     */
	 ldr r0, =0xd00001E0
	 ldr r2, =0xd0000218
RCV:
	 str	r1, [r0]
	 add r0, r0, #0x8
	 cmp r0, r2
	 ble RCV


	/* Program CKE x8 pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dckex8pslew0 - cr0_dckex8pslew3) and (cr0_dckex8nslew0 - cr0_dckex8nslew3) 
     */
	 ldr r0, =0xd0000230
	 ldr r2, =0xd0000268
CKE_x8:
	 str	r1, [r0]
	 add r0, r0, #0x8
	 cmp r0, r2
	 ble CKE_x8


	/* Program CKE x16 pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dckex16pslew0 - cr0_dckex16pslew3) and (cr0_dckex16nslew0 - cr0_dckex16nslew3) 
     */
	 ldr r0, =0xd0000270
	 ldr r2, =0xd00002A8
CKE_x16:
	 str	r1, [r0]
	 add r0, r0, #0x8
	 cmp r0, r2
	 ble CKE_x16


	/* Program CS# x8 pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dcsx8pslew0 - cr0_dcsx8pslew3) and (cr0_dcsx8nslew0 - cr0_dcsx8nslew3) 
     */
	 ldr r0, =0xd00002B8
	 ldr r2, =0xd00002F0
CS_x8:
	 str	r1, [r0]
	 add r0, r0, #0x8
	 cmp r0, r2
	 ble CS_x8


	/* Program CS# x16 pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dcsx16pslew0 - cr0_dcsx16pslew3) and (cr0_dcsx16nslew0 - cr0_dcsx16nslew3) 
     */
	ldr r0, =0xd00002F8
	ldr r2, =0xd0000330
CS_x16:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CS_x16


	/* Program CK CK# x8 pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dckx8pslew0 - cr0_dckx8pslew3) and (cr0_dckx8nslew0 - cr0_dckx8nslew3) 
     */
	ldr r0, =0xd0000340
	ldr r2, =0xd0000378
CK_x8:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CK_x8


	/* Program CK CK# x16 pull-up and pull-down Slew Lookup table registers 
	 * (cr0_dckx16pslew0 - cr0_dckx16pslew3) and (cr0_dckx16nslew0 - cr0_dckx16nslew3) 
     */
	ldr r0, =0xd0000380
	ldr r2, =0xd00003B8

CK_x16:
	str	r1, [r0]
	add r0, r0, #0x8
	cmp r0, r2
	ble CK_x16


/* Flag Slew Programmed register as done */
	ldr r0, =CR0_SLEWPROGRAMMED
	ldr r1, =0x00000001
	str	r1, [r0]

/* cr0_ovrrideh: turn off h override, 0x0 */
	
	ldr r1, =0x00000000