sysalib.s

ixp2400 bsp for vxworks

                ldr r1, =0x0
pci_cmd_fifo_flush_loop:
                str     r1, [r0]
                add r3, r3, #1
                cmp r3, #8
                bne pci_cmd_fifo_flush_loop

#if A0_REV
                /* set PCI rcomp registers*/
                ldr r0, =IXP2400_PCI_RCOMP_OVER
                ldr r1, =0x153239
                str r1, [r0]

                /* set slave's pci rcomp register within 2000 cycles. */
                ldr r0, =0xDA200060
                ldr r1, =0x153239
                str r1, [r0]
#endif
#endif

/******************************************************************************/

clock_setup:

#if A0_REV
        ldr r0, =SYS_CLK_M
        ldr r1, [r0]
        and r1, r1, #0xFF
        ldr r4, =SRAM_150MHZ_DIVISOR
        cmp r1, #0x55
        bne sram_divisor_set
#endif
        ldr r4, =SRAM_200MHZ_DIVISOR

sram_divisor_set:
/* now set the operating freq. for SRAM/SDRAM interface */
        ldr r0, =IXP2400_CLOCK_CONTROL      /* Load the address of the clock control Register in r0 */
        ldr r1, [r0]                        /* store old value in r1 */
        ldr r2, =(~(0xF00FF))
        and r1, r1, r2                      /* clear sdram and sram divisor default value */
        orr r1, r1, #(SDRAM_DIVISOR << 16)  /* Set SDRAM clock ratio */
        mov r5, r4, lsl #4
        orr r1, r1, r5                      /* Set SRAM channel 1 clock ratio */
        orr r1, r1, r4                      /* Set SRAM channel 0 clock ratio */
        mov r3, #0x0
        mcr p15, 0, r0, c7, c10, 4          /* DCU drain instruction */
        b clk_stab

        /* wait for some time so that clock gets stabilized
         * make this code aligned at 32 bytes so that it is
         * aligned on prefatch boundary
         */
        .p2align 5

clk_stab:
        str r1, [r0]                        /* Store to clock control Register */
clk_stab_loop:
        add r3, r3, #1
        cmp r3, #0x200
        bne clk_stab_loop
        b clk_stab_done

        .p2align 5

clk_stab_done:
        /*set the DRAM I/O CSRs*/
        ldr r0, =IXP2400_DDR_RDDLYSEL_RECEN
        ldr r1, =DDR_RDDLYSEL_RECEN_VAL
        str r1, [r0]

        ldr r0, =IXP2400_DDR_RX_DLL
        ldr r1, =DDR_RX_DLL_VAL
        str r1, [r0]

        ldr r0, =IXP2400_DDR_RX_DESKEW
        ldr r1, =DDR_RX_DESKEW_VAL
        str r1, [r0]

        /* Rcomp Initialisation, Select Stength for Pin Groups */
        ldr r0, =CR0_DSTRENGTHSEL
        ldr r1, =0x036db6db           /* rcv 1.5x rest 1.5x */
        str r1, [r0]

        /* Program Rcomp offset registers to 0 (until characterised values are available)
         * Bit[15] = Sign for pulldown
         * Bit[14:8] = Value for Pulldown
         * Bit[7] = Sign for pullup
         * Bit[6:0] = Value for Pullup
         */
        ldr r1, =0x00000000

        ldr r0, =CR0_DDQRCOMP        /* DQ/DQS offset*/
        str  r1, [r0]

        ldr  r0, =CR0_DCTLRCOMP      /* MA/BA/RAS#/CAS#/WE# offset*/
        str  r1, [r0]

        ldr r0, =CR0_DRCVRCOMP       /* RCV offset*/
        str  r1, [r0]

        ldr r0, =CR0_DCKERCOMP       /* CKE offset*/
        str  r1, [r0]

        ldr r0, =CR0_DCSRCOMP        /* CS# offset*/
        str  r1, [r0]

        ldr r0, =CR0_DCKRCOMP        /* CK/CK# offset [31:16 for X16, 15:0 for x8]*/
        str  r1, [r0]

        /* Select x8 or x16 slew compensation for CKE, CS, CK */
        ldr r0, =CR0_DX8X16CKECSCKSEL
        ldr r1, =0x11111111          /* for x8 slew compensation*/
        str  r1, [r0]

        /* Select rcomp Period */
        ldr r0, =CR0_RCOMPPRD
        ldr r1, =0x00000000          /* for period = 2097152 clock cyles*/
        str  r1, [r0]

        /* set Dig Filter Clamp */
        ldr r0, =CR0_DIGFIL
        ldr r1, =0x00000000          /* for no filter*/
        str  r1, [r0]

        /* Program DDR DQ/DQS pull-up and pull-down Slew Lookup table registers
         * (cr0_ddqpslew0 - cr0_ddqpslew3) and (cr0_ddqnslew0 - cr0_ddqnslew3)
         */
        ldr r1, =0xcccccccc
        ldr r0, =0xd0000150
        ldr r2, =0xd0000188
DQ_DQS:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble DQ_DQS

        /* Program MA/BA/RAS#/CAS#/WE# pull-up and pull-down Slew Lookup table registers
         * (cr0_dctlpslew0 - cr0_dctlpslew3) and (cr0_dctlnslew0 - cr0_dctlnslew3)
         */
        ldr r0, =0xd0000198
        ldr r2, =0xd00001D0
MA_BA_RAS_CAS_WE:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble MA_BA_RAS_CAS_WE

        /* Program RCV pull-up and pull-down Slew Lookup table registers
         * (cr0_drcvpslew0 - cr0_drcvpslew3) and (cr0_drcvnslew0 - cr0_drcvnslew3)
         */
        ldr r0, =0xd00001E0
        ldr r2, =0xd0000218
RCV:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble RCV

        /* Program CKE x8 pull-up and pull-down Slew Lookup table registers
         * (cr0_dckex8pslew0 - cr0_dckex8pslew3) and (cr0_dckex8nslew0 - cr0_dckex8nslew3)
         */
        ldr r0, =0xd0000230
        ldr r2, =0xd0000268
CKE_x8:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble CKE_x8

        /* Program CKE x16 pull-up and pull-down Slew Lookup table registers
         * (cr0_dckex16pslew0 - cr0_dckex16pslew3) and (cr0_dckex16nslew0 - cr0_dckex16nslew3)
         */
        ldr r0, =0xd0000270
        ldr r2, =0xd00002A8
CKE_x16:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble CKE_x16

        /* Program CS# x8 pull-up and pull-down Slew Lookup table registers
         * (cr0_dcsx8pslew0 - cr0_dcsx8pslew3) and (cr0_dcsx8nslew0 - cr0_dcsx8nslew3)
         */
        ldr r0, =0xd00002B8
        ldr r2, =0xd00002F0
CS_x8:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble CS_x8

        /* Program CS# x16 pull-up and pull-down Slew Lookup table registers
         * (cr0_dcsx16pslew0 - cr0_dcsx16pslew3) and (cr0_dcsx16nslew0 - cr0_dcsx16nslew3)
         */
        ldr r0, =0xd00002F8
        ldr r2, =0xd0000330
CS_x16:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble CS_x16

        /* Program CK CK# x8 pull-up and pull-down Slew Lookup table registers
         * (cr0_dckx8pslew0 - cr0_dckx8pslew3) and (cr0_dckx8nslew0 - cr0_dckx8nslew3)
         */
        ldr r0, =0xd0000340
        ldr r2, =0xd0000378
CK_x8:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble CK_x8

        /* Program CK CK# x16 pull-up and pull-down Slew Lookup table registers
         * (cr0_dckx16pslew0 - cr0_dckx16pslew3) and (cr0_dckx16nslew0 - cr0_dckx16nslew3)
         */
        ldr r0, =0xd0000380
        ldr r2, =0xd00003B8

CK_x16:
        str r1, [r0]
        add r0, r0, #0x8
        cmp r0, r2
        ble CK_x16

/* Flag Slew Programmed register as done */
        ldr r0, =CR0_SLEWPROGRAMMED
        ldr r1, =0x00000001
        str r1, [r0]

/* cr0_ovrrideh: turn off h override, 0x0 */
        ldr r1, =0x00000000
        ldr r0, =CR0_OVRRIDEH
        str r1, [r0]

/* cr0_ovrridev: turn off v override, 0x0 */
        ldr r0, =CR0_OVRRIDEV
        str r1, [r0]

/* De-Select Test Mode (cr0_jt_config) at address offset 0x3C0
 * User Overide RCOMP settings
 */
        ldr r0, =CR0_JT_CONFIG
        str r1, [r0]

/* wait for 4000 cycles*/
        mov r0, #0x0
wait_ddr_io:
        add r0, r0, #1
        cmp r0, #2000
        bne wait_ddr_io

/******************************************************************************/
/* Clear Low Memory */
        ldr     r0, =LOCAL_MEM_LOCAL_ADRS
        ldr     r1, =FUNC(probeInit)
        sub     r1, r1, r0
        sub     r1, r1, #64
        mov     r2, #0
        bl      FUNC(bfill)

/* Copy Initial MMU Tables to Low Memory */
        ldr     r0, =_probeInitMmuTable
        ldr     r1, =(LOCAL_MEM_LOCAL_ADRS + MMU_TRANSLATION_BASE)
        ldr     r2, =0x4400
        bl      FUNC(bcopy)

/* Enable access to all coprocessor registers*/
        ldr     r1, =0x2001
        mcr     p15, 0, r1, c15, c1, 0

        mcr     p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
        CPWAIT  (r0)                    /* wait for the write to happen */

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr     p15, 0, r1, c7, c7, 0
        CPWAIT  (r1)                    /* Wait */

/* flush instruction and data TLBs */
        mcr     p15, 0, r1, c8, c7, 0
        CPWAIT  (r1)                    /* Wait */

/* Enable Instruction Cache */
        mrc     p15, 0, r1, c1, c0, 0   /* Read Control Register*/
        orr     r1, r1, #0x1000         /* Set I-Cache bit */
        mcr     p15, 0, r1, c1, c0, 0   /* Write Back Control Register */
        CPWAIT  (r1)                    /* Wait */

/* Set Translation Table Base */
        ldr     r1, =(LOCAL_MEM_LOCAL_ADRS + MMU_TRANSLATION_BASE)
        mcr     p15, 0, r1, c2, c0, 0   /* Set Translation Table Base Register */
        CPWAIT  (r1)                    /* Wait */

/* Invalidate Instruction, Data TLBs */
        mcr     p15, 0, r1, c8, c7, 0   /* Flush I & D TLBs*/
        CPWAIT  (r1)                    /* Wait */

/* Set Domain Access Control Register */
        ldr     r1, =0xffffffff         /* Set All 16 domains to manager access */
        mcr     p15, 0, r1, c3, c0, 0   /* Set Domain Permissions */
        CPWAIT  (r1)                    /* Wait */

/* Enable MMU */
        mrc     p15, 0, r1, c1, c0, 0   /* Read Control Register */
        orr     r1, r1, #0x00000001     /* Enable MMU */

        mcr     p15, 0, r1, c1, c0, 0   /* Write Back the Control Register */
        CPWAIT  (r1)                    /* Wait */

/* Drain Write/Fill Buffers */
        mcr     p15, 0, r1, c7, c10, 4  /* Drain */
        CPWAIT  (r1)                    /* Wait */

/* Enable Data Cache */
        mrc     p15, 0, r1, c1, c0, 0   /* Read Control Reg */
        orr     r1, r1, #0x00000004     /* Enable Data Cache */
        mcr     p15, 0, r1, c1, c0, 0   /* Write Back */
        CPWAIT  (r1)                    /* Wait */

/* Enable Branch Target Buffer */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000800     /* Enable BTB */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */
        CPWAIT(r0)                      /* Wait */

/******************************************************************************/
        mov     r0, #BOOT_CLEAR /* pass startType */

/* now call usrInit */
        b       FUNC(usrInit)

#else /* ! INCLUDE_HSI_PROBE */

        .text
        .align 4

/*******************************************************************************
*
* sysInit - start after boot
*
* This routine is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting.  It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit().  This
* stack is used only by usrInit() and is never used again.  Memory for the
* stack must be accounted for when determining the system load address.