sysalib.s

ixp2400 bsp for vxworks

/* sysALib.s - ixdp2400 system-dependent routines */

/* Copyright 2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,15jan03,scm  corrections to support INCLUDE_HSI_PROBE...
01a,05apr02,vgd  created from BRH BSP.
*/

/*
DESCRIPTION
This module contains system-dependent routines written in assembly
language.

This module must be the first specified in the \f3ld\f1 command used to
build the system.  The sysInit() routine is the system start-up code.

INTERNAL
Many routines in this module doesn't use the "c" frame pointer %r11@ !
This is only for the benefit of the stacktrace facility to allow it
to properly trace tasks executing within these routines.

SEE ALSO:
.I "ARM Architecture Reference Manual"
*/

#define _ASMLANGUAGE

#include "vxWorks.h"
#include "regs.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"
#include "arch/arm/excArmLib.h"
#include "sysLib.h"
#include "config.h"

        .data
        .globl  VAR(copyright_wind_river)
        .long   VAR(copyright_wind_river)


        /* internals */

        .globl  FUNC(sysInit)                /* start of system code */
        .globl  FUNC(sysIntStackSplit)
        .globl  FUNC(sysGetTransTblBase)

        .globl  FUNC(sysWrite16)             /* routine to do STRH */
        .globl  FUNC(sysRead16)              /* routine to do LDRH */

        .globl  FUNC(swap32)                 /* routine to swap bytes in 32 bit int */
        .globl  FUNC(swap16)                 /* routine to swap bytes in 16 bit int */

        .globl  FUNC(singleFlashBootLow)
        .globl  FUNC(singleFlashBootHi)

        /* externals */

        .extern FUNC(usrInit)                /* system initialization routine */
        .extern FUNC(vxSvcIntStackBase)      /* base of SVC-mode interrupt stack */
        .extern FUNC(vxSvcIntStackEnd)       /* end of SVC-mode interrupt stack */
        .extern FUNC(vxIrqIntStackBase)      /* base of IRQ-mode interrupt stack */
        .extern FUNC(vxIrqIntStackEnd)       /* end of IRQ-mode interrupt stack */


#if defined(INCLUDE_HSI_PROBE)
        .globl  FUNC(probeInit)              /* start of system code */
        .extern FUNC(bcopy)
        .extern FUNC(bfill)

/*
 
- Caching Uint requires MMU
- The portion of the cache is used as internal data RAM, and since cache unit
  requires MMU, the MMU should be ON in order to access the internal data RAM.
*/

#ifdef _DIAB_TOOL

PT_ENTRY: .macro base,x,ap,p,d,c,b,total
        .if total
                .if total <= 0x40
                        .long ((base<<20)|(x<<12)|(ap<<10)|(p<<9)|(d<<5)|(c<<3)|(b<<2)|2)
                        PT_ENTRY (base+1),x,ap,p,d,c,b,(total-1)
                .else
                        .if total <= 0x256
                                PT_ENTRY base,x,ap,p,d,c,b,0x40
                                PT_ENTRY (base+0x40),x,ap,p,d,c,b,(total-0x40)
                        .else
                                PT_ENTRY base,x,ap,p,d,c,b,0x256
                                PT_ENTRY (base+0x256),x,ap,p,d,c,b,(total-0x256)
                        .endif
                .endif
        .endif
        .endm

/* Coarse page descriptor contains 14 bits, since it is easy to manipulate
 * the hex values, here the addr is shifted only by 12 bits, instead of 14bits.
 * So make sure that bit 11 and 10 are set to correctly in  options.
 * Bit 11 and 10 in options should contain the 2 LSBs from the coarse page address
 */

COARSE_ENTRY: .macro addr,options
        .long ((addr<<12)|options)
        .endm

/*
 * Extended Small Page Tables
 */

EX_ENTRY: .macro base,x,ap,c,b,total
        .if total
                .if total <= 0x40
                        .long ((base<<12)|(x<<6)|(ap<<4)|(c<<3)|(b<<2)|3)
                        EX_ENTRY (base+1),x,ap,c,b,(total-1)
                .else
                        .if total <= 0x256
                                EX_ENTRY base,x,ap,c,b,0x40
                                EX_ENTRY (base+0x40),x,ap,c,b,(total-0x40)
                        .else
                                EX_ENTRY base,x,ap,c,b,0x256
                                EX_ENTRY (base+0x256),x,ap,c,b,(total-0x256)
                        .endif
                .endif
        .endif
        .endm

INVALID_ENTRY: .macro total
        .if total
                .if total <= 0x40
                        .long (0)
                        INVALID_ENTRY (total-1)
                .else
                        .if total <= 0x256
                                INVALID_ENTRY 0x40
                                INVALID_ENTRY (total-0x40)
                        .else
                                INVALID_ENTRY 0x256
                                INVALID_ENTRY (total-0x256)
                        .endif
                .endif
        .endif
        .endm

#else /* GNU */

.MACRO PT_ENTRY base,x,ap,p,d,c,b,total=0
.if \total
   .if \total <= 0x40
      .long (\base << 20) | (\x << 12) | (\ap << 10) | (\p << 9) | (\d << 5) | (\c << 3) | (\b << 2) | 2
      PT_ENTRY "(\base+1)",\x,\ap,\p,\d,\c,\b,"(\total-1)"
   .else
       .if \total <= 0x256
           PT_ENTRY \base,\x,\ap,\p,\d,\c,\b,0x40
           PT_ENTRY "(\base+0x40)",\x,\ap,\p,\d,\c,\b,"(\total-0x40)"
       .else
           PT_ENTRY \base,\x,\ap,\p,\d,\c,\b,0x256
           PT_ENTRY "(\base+0x256)",\x,\ap,\p,\d,\c,\b,"(\total-0x256)"
       .endif
   .endif
.endif
.ENDM

/* Coarse page descriptor contains 14 bits, since it is easy to manipulate
 * the hex values, here the addr is shifted only by 12 bits, instead of 14bits.
 * So make sure that bit 11 and 10 are set to correctly in  options.
 * Bit 11 and 10 in options should contain the 2 LSBs from the coarse page address
 */

.MACRO COARSE_ENTRY addr=0,options=0
   .long ((\addr << 12) | \options)
.ENDM

/*
 * Extended Small Page Tables
 */

.MACRO EX_ENTRY base,x,ap,c,b,total=0
.if \total
   .if \total <= 0x40
      .long (\base << 12) | (\x << 6) | (\ap << 4) | (\c << 3) | (\b << 2) | 3
      EX_ENTRY "(\base+1)",\x,\ap,\c,\b,"(\total-1)"
   .else
       .if \total <= 0x256
           EX_ENTRY \base,\x,\ap,\c,\b,0x40
           EX_ENTRY "(\base+0x40)",\x,\ap,\c,\b,"(\total-0x40)"
       .else
           EX_ENTRY \base,\x,\ap,\c,\b,0x256
           EX_ENTRY "(\base+0x256)",\x,\ap,\c,\b,"(\total-0x256)"
       .endif
   .endif
.endif
.ENDM

.MACRO INVALID_ENTRY total=0
.if \total
   .if \total <= 0x40
       .long (0)
       INVALID_ENTRY "(\total-1)"
   .else
       .if \total <= 0x256
           INVALID_ENTRY 0x40
           INVALID_ENTRY "(\total-0x40)"
       .else
           INVALID_ENTRY 0x256
           INVALID_ENTRY "(\total-0x256)"
       .endif
   .endif
.endif
.ENDM

#endif /* _DIAB_TOOL */

        .data
        .align 4

_probeInitMmuTable:

/*make SDRAM(512MB) used by vxWorks, microengines and drivers cacheable, buffereable*/
PT_ENTRY 0x0,0,3,0,0,1,1,0x200

/*IXP2400 supports 2GB of DRAM, but our SDRAM module is only 512MB.
 *so make the rest of memory invalid
 */
INVALID_ENTRY 0x600

/*make SRAM (1GB)rw, cacheable and bufferable*/
PT_ENTRY 0x800,0,3,0,0,1,1,0x400

/* Make CSR, flash and PCI Mem as rw, non-cacheable and non-bufferable. total 1GB*/
PT_ENTRY 0xc00,1,3,0,0,0,1,0x400

	.text
	.align 4

/*******************************************************************************
*
* sysInit/probeInit - (standalone alone  debug version with visionProbe) 
*                   - start after boot
*
* This routine is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting.  It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit().  This
* stack is used only by usrInit() and is never used again.  Memory for the
* stack must be accounted for when determining the system load address.
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A

* sysInit ()              /@ THIS IS NOT A CALLABLE ROUTINE @/

*/

_ARM_FUNCTION(probeInit)
_ARM_FUNCTION(sysInit)

/* Disable Interrupts */
        MRS     r1, cpsr                /* get current status */
        ORR     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */
        MSR     cpsr, r1

/* Interrupts Disabled */
        ldr     r1, =IXP2400_IRQ_ENABLE_CLR_REG /* Mask Interrupts */
        ldr     r2, =IXP2400_MASK_ALL_INT
        str     r2, [r1]

        adr     sp, FUNC(probeInit)     /* initialise stack pointer */
        mov     fp, #0                  /* initialise frame pointer */

/*** Disable Write Buffer Coalescing ***/
        mcr     p15, 0, r1, c7, c10, 4  /* Drain write/fill buffers */
        CPWAIT  (r1)                    /* wait for the write to happen */
        CPWAIT  (r1)                    /* wait for the write to happen */

        mrc     p15, 0, r1, c1, c0, 1   /* Read Auxiliary Control Reg */
        orr     r1, r1, #0x00000001     /* Disable Coalescing */
        mcr     p15, 0, r1, c1, c0, 1   /* Write Auxiliary Control Reg */
        CPWAIT  (r1)                    /* wait for the write to happen */

#if (_BYTE_ORDER == _BIG_ENDIAN)
        mrc     p15, 0, r1, c1, c0, 0   /* Read Control Reg */
        orr     r0, r1, #0x80           /* set bit7, enable big endian */
        mcr     p15, 0, r1, c1, c0, 0   /* Write Control Reg */
#endif

        ldr r0,  =IXP2400_STRAP_OPTIONS /* Load the address of the strap options Register in r0*/
        ldr r1,  [r0]                   /* get value in r1*/
        and r9,  r1, #CFG_PCI_BOOT_HOST /* save master/slave id in r9*/
        and r10, r1, #CFG_PROM_BOOT     /* save single/dual boot rom in r10*/

/*********slowPort config**********************/
	/*configure Slowport*/

	/*The work around for sausolito bUg #1199 is to set teh clock doivisor
	 *in SP_CCR to 1. as the default is 1:1 no change needed in our code
	 */
		/* read the value of SP_RTC and put it in WTC register*/
                ldr r3, =IXP2400_SP_RTC1
                ldr r1, [r3]
                ldr r3, =IXP2400_SP_WTC1 /* Load the address of the slow port write timing control Register in r0*/
                str r1, [r3]     /* Store to slow port write timing control Register*/

                ldr r3, =IXP2400_SP_WTC2 /* Load the address of the slow port write timing control Register in r0*/
                str r1, [r3]     /* Store to slow port write timing control Register*/

                ldr r3, =IXP2400_SP_RTC2 /* Load the address of the slow port write timing control Register in r0*/
                str r1, [r3]     /* Store to slow port write timing control Register*/

                ldr r3, =IXP2400_MISC_CONTROL   /* Load the address of the misc control Register in r0*/
                ldr r1, [r3]                    /* store old value in r1*/
                ldr r2, =FLASH_WRITE_ENABLE
                orr r1, r1, r2                  /* make flash write enable for flash utility*/
                str r1, [r3]                    /* Store to misc control Register*/

/*******PCI rcomp reg setting ****************/
#ifdef INCLUDE_PCI
                cmp r9, #CFG_PCI_BOOT_HOST /*if not master NPU jump*/
                bne pci_reset_out

                ldr r0, =IXP2400_RESET_0
                ldr r1, [r0]
                orr r1, r1, #PCIRST
                orr r1, r1, #RESET_PCI
                str r1, [r0]
                ldr r3, =0x0
pci_reset_loop:
                add r3, r3, #1
                cmp r3, #200
                bne pci_reset_loop

pci_reset_out:
                /* take pci out of reset*/
                ldr r0, =IXP2400_RESET_0
                ldr r1, [r0]
                bic r1, r1, #PCIRST
                bic r1, r1, #RESET_PCI
                str r1, [r0]

                /* 8 dummy writes to flush pci cmd fifo*/
pci_cmd_fifo_flush:
                mov r3, #0x0
                ldr r0, =IXP2400_MAILBOX0