target.nr

ixp2400 bsp for vxworks

The default physical to virtual mapping is defined as:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 5
Physical to Virtual Address Mapping
.sp .25
Physical Addresses	Virtual Addresses	Comments
_
1e000000-20000000	00000000-02000000	SDRAM used by VxWorks
00000000-1e000000	02000000-20000000	SDRAM used by VxWorks
.TE
.SS "RAM size"
The BSP supports the default configuration of 512 MB SDRAM; of
this, the upper 32 MB are remapped to virtual address 0 and are
available for use by VxWorks.  The lower 480 MB are mapped to
0x02000000 and are uncached.  This configuration may be changed by 
modifying the BSP.  For more details, see "Cache/MMU Considerations".

The BSP supports 8 MB of SRAM although, this is not included in
the VxWorks memory pool.  Use of this memory must be managed by
application-specific code.


.SS "Flash Memory"
A driver is provided to support access to the flash memory and the
use of a section of it as NVRAM.

.SS "ROM_COPY_SIZE Macro"
ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
and this is defined as 2MB in the BSP. This ROM_COPY_SIZE may have to be
increased in case the application is also built with the vxworks image.

.SS "SINGLE_BOOTROM Macro"
The dual NPUs on the IXDP2400 Development platform can be booted either in
Single Flash mode or Dual Flash Mode. When using the single Flash mode, the macro
SINGLE_BOOTROM should be defined to 1 when bootRom and VxWorks images are built. 
When building rommable vxworks images, this macro needs to be defined to 0.


.SS "NetROM Support"
The BSP supports the use of NetROM in place of flash
memory.

.SS "Timers and Timestamp support"
The ixp2400 contains four 32-bit timers (timer 1thru 4) capable of interrupting
the ixp2400.Timer 2 is devoted to the vxWorks system clock, while
timer 3 is dedicated to the auxillary timer.  Timestamps are derived from the 
VxWorks system clock timer.Timer 1 is used for Delays in the BSP. Timer4 is left
for use by the Application. Timer 4 also has the capability of being configured 
as Watchdog Time.

.bS
                        _______
hardware                TIMER 2
clock                   _______
                           |
interface -------------------------------
                   |             |
                   |             |
software        _______     _____________
clock(s)        sysClk      timeStampClk
                _______     _____________
.bE

.bS
                        _______
hardware                TIMER 3
clock                   _______
                           |
interface -------------------------------
                                  |
                                  |     
software                        ______
clock(s)                        auxClk
                                ______
.bE


.SS "Special routines"
There is a 4 character Alphanumeric display on each NPU, on the IXDP2400 
Development Platform base board,which may aid in user debug.This is mapped 
via a memory mapped register on the slow port located in a CPLD.A routine 
to display various characters sysLEDDisplay() is provided in the BSP.Macros 
to display various alpha numeric characters are provided in the BSP-specific 
header file, ixdp2400.h.

.bS
 4 Char LCD Display

         			
       ----------
       |        |Egress NPU 4 char 
       |--------|LCD panel
       |        |
       |--------| 
       |        | 
       |--------|
       |        |
       ----------
       ----------
       |        |Ingress NPU 4 char 
       |--------|LCD panel
       |        |
       |--------| 
       |        | 
       |--------|
       |        |
       ----------

      
.bE


.SS "Divide by Zero Exception"
The ARM architecture does not provide for an integer divide by zero
exception.  Consequently, no exception is generated when an integer
divide by zero operation is performed programmatically.


.SS "IXDP2400 PLATFORM BASE BOARD DETAILS"
.SS "Board Layout"
The diagrams below show the relevant jumpers for VxWorks configuration.
.bS
_________________________________________________________________________
| +---------+ +---------+ +---------+   +---------+        +------+     |
| |E-Power  | |I-Power  | |E-NetRom |   |I-NetRom |        | E-LCD|     |
| |Connector| |Connector| +---------+   +---------+	   |      |     |
| +---------+ +---------+ +---------+   +---------+        +------+     |
|	   +-+	          |E-Flash  |   | I-Flash |        |      |     |
|   SW0301 | | 	          +---------+   +---------+	   | I-LCD|	|
|          +-+           +---------+  +---------+          +------+     |
|		         |  E-CPLD |  | I-CPLD  |                       |
|          +-+           |         |  |         |                       |
|   SW2701 | |    SW0201 +---------+  +---------+                       |
|	   +-+	  +----+                                                | 
|                 +----+         +----------+                           |   
|          +-+    +----+ +----+  |          |                           |
|   SW2702 | |    +----+ +----+  |  SF I/F  |                           |
|          +-+    SW2002 SW2001  |          |           	        |	  	 
|               +-------+        +----------+              +--------+   |
|               |E-JTAG |                                  |I-JTAG  |   |
|               +-------+      +----------+   +----------+ +--------+   |
|                              |          |   |          |              |
|                              | Egress   |   | Ingress  |              |
|                              | NPU      |   | NPU      |              |
|                              | IXP2400  |   | IXP2400  |              |
|                              |          |   |          |              |
|                              +----------+   +----------+              |
|                                                                       |
|                                 +------------+                        |
|                                 |            |                        |
|                                 | Media I/F  |                        |
|                                 |            |                        |
|                                 +------------+                        |
|_______________________________________________________________________|

.SS "Front Panel:"
_________________________________________________________________________
|	Mgmt Ports							 |
|	+---------+----------+		Reset   NPU   Status	Power	 |
|	| Egress  | Ingress  |                                           |
|	| Network | Network  |		  O      ==     ==	 O 	 |
|	+---------+----------+                 Egress Ingress    On      |
|	| Egress  | Ingress  |                                           |  
|	| Console | ConSole  |                                           |  
|       +---------+----------+	    				         |
|________________________________________________________________________|


.bE
Key:
    E       A prefix of 'E' indicates that the component is for the Egress NPU
    I       A prefix of 'I' indicates that the component is for the Ingress NPU


.SS "Switch Settings"
The following switches are relevant to VxWorks configuration.

SW2001 and SW2002
These are used to select the NPU speed. sw2001 is also used to select the 
reset and boot mechanism
Switch SW2001
.TS E
Bit#	Decription					
sw1	On : 
	Off: 		
sw2	On : 
	Off: 
sw3	On : 
	Off: 
sw4	On : Reset provided by IXDP2400
	Off: Reset provide by CPCI backplane
sw5	On : External PROM on 21555  
	Off: No external PROM on 21555
sw6	On : 21555 Primary PCI - 64 bit
	Off: 21555 Primary PCI - 32 bit
sw7	On : Ingress NPU boot from PCI
	Off: Ingress NPU boot from Flash 
sw8	On : Egress NPU boot from PCI
	Off: Egress NPU boot from Flash
.TE
Switch SW2002
Bit#	Decription			
sw1	On : System Clock M setting: 0
	Off: System Clock M setting: 2		
sw2	On : System Clock M setting: 0
	Off: System Clock M setting: 4
sw3	On : System Clock M setting: 0
	Off: System Clock M setting: 8
sw4	On : System Clock M setting: 0
	Off: System Clock M setting: 16
sw5	On : System Clock M setting: 0
	Off: System Clock M setting: 32
sw6	On : System Clock M setting: 0
	Off: System Clock M setting: 64
sw7	On : System Clock M setting: 0
	Off: System Clock M setting: 128
sw8	On : System Clock M setting: 0
	Off: System Clock M setting: 256

Switch SW0201
Sw0201 is used to set the PCI window sizes.
Bits 1,2 Control the Ingress PCI SRAM Window Size
.TS E
 sw1 sw2 size
 On  On  32M
 Off On  64M
 On  Off 128M
 Off Off 256M     	
.TE
Bits 3,4 control the Ingress PCI DDR Window Size
 sw3 sw4 size
 On  On  128M
 Off On  256M
 On  Off 512M
 Off Off 1024M     

Bits 5,6 control the Egress PCI SRAM Window Size
.TS E
 sw5 sw6 size
 On  On  32M
 Off On  64M
 On  Off 128M
 Off Off 256M     	
.TE

bits 7,8 control the Egress PCI DDR Window Size
.TS E
 sw3 sw4 size
 On  On  128M
 Off On  256M
 On  Off 512M
 Off Off 1024M     
.TE
NOTE:By Default all the settings are set to 600Mhz

SW2701 and SW2702
These switches are used to select the JTAG/normal operation.

To set Both Egress and Ingress NPUs in Normal mode:
.TS E
sw#  sw2701 sw2702		
sw1  On	    On
sw2  On     Off
sw3  On     Off
sw4  Off    Off
sw5  Off    Off
sw6  Off    Off
sw7  Off    Off
sw8  Off    Off
.TE 

To set Both Egress and Ingress NPUs in BSCAN JTAG mode:
.TS E
sw#  sw2701 sw2702		
sw1  On	    On
sw2  On     On
sw3  On     On
sw4  Off    On
sw5  Off    On
sw6  Off    Off
sw7  Off    Off
sw8  Off    On
.TE

To set Both Egress and Ingress NPUs in ICE JTAG mode:
.TS E
sw#  sw2701 sw2702		
sw1  Off    Off
sw2  Off    Off
sw3  Off    Off
sw4  Off    Off
sw5  Off    On
sw6  Off    On
sw7  On     On
sw8  On     Off
.TE

To set Egress is ICE JTAG MODE and INgress in NORMAL Mode:
.TS E
sw#  sw2701 sw2702		
sw1  On	    Off
sw2  Off    Off
sw3  On     Off
sw4  Off    Off
sw5  Off    Off
sw6  Off    Off
sw7  Off    On
sw8  On     Off
.TE

To Set Egress in Normal Mode and Ingress in ICE JTAG Mode:
.TS E
sw#  sw2701 sw2702		
sw1  Off    On
sw2  On     Off
sw3  Off    Off
sw4  Off    Off
sw5  Off    Off
sw6  Off    On
sw7  On     Off
sw8  Off    Off
.TE

SW2701 Bit Definitions:
Bit 1:	Egress PCI Rst# <-> Ingress sys rst
Bit 2: 	Sys_rst# <-> Egress sys rst
Bit 3: 	TRST# <-> Egress TRST#
Bit 4: 	Ingress QDR TDO <-> TDO
Bit 5:	JTAG Buffer Tck <-> Tck
Bit 6:	JTAG Buffer Tck <-> Tms
Bit 7:	Ingress sys rst <-> Ingress ICE rst
Bit 8: 	Egress sys rst <-> Egress ICE rst

SW2703 Bit Definitions:
Bit 1:	21555 TRST# <-> Egress TRST
Bit 2:	JTAG Buffer Disable
Bit 3:	JTAG Bypass Egress DDR
Bit 4: 	JTAG Bypass Ingress DDR
Bit 5:	JTAG Bypass Media
Bit 6:	Ingress TDI <-> Ingress ICE TDI
Bit 7:	Egress TDI <-> Egress ICE TDI
Bit 8:	QDR JTAG Bypass

SW0301
This switch is used to select netrom/flash boots.Bits 1-6 are should always be OFF
To boot EGRESS and INgress from Flash
sw7 - On
sw8 - On

To Boot Egress nad Ingress from netrom
sw7- Off
sw8- Off

To boot Egress from flash and Ingress from Netrom
sw7- Off
sw8 - On

To boot Egress from Netrom and Ingress from Flash
sw7-On
sw8- Off

SW0301 Bit Definitions:
Bit 1:	Reserved
Bit 2:	Reserved
Bit 3:	Misc. CPLD register
Bit 4:	Misc. CPLD register
Bit 5:	Misc. CPLD register
Bit 6:	Misc. CPLD register
Bit 7:	Ingress NetRom / Flash  (On = Flash; Off = NetRom)
Bit 8:	Egress NetRom / Flash  	(On = Flash; Off = NetRom)

.SS "Errata"
IXP2400 has a bug because of which you can not have any page with
attributes XCB = 000. That's why all the page attributes are set to
XCB = 101. Because of this workaround sysEnd.c has been changed so
that fei driver doesn't use cacheDmaMallo (which returns a pointer
of page with attributes XCB = 000). Please see IXP2400 errata for
further clarification.

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration."


.SH "BIBLIOGRAPHY"
.I "IXP2400 Programmer's Refernce Manual",
.I "Intel XScale Microarchitecture Programmer Model for Big Endian",
.I "Intel XScale Core Developers Manual",
.I "Intel 82559 Fast Ethernet Multifunction PCI/Card Bus Controller",
.I "Intel XScale Microarchitecture, Programmers Reference Manual",
.I "PCI Local Bus Specification, Revision 2.2 (www.pcisig.com)",
.I "GNUPro Toolkit Documentation",