target.nr

ixp2400 bsp for vxworks

'\" t
.so wrs.an
.\" ixdp2400/target.nr - target-specific documentation
.\"
.\" Copyright 2001 Wind River Systems, Inc.
.\"
.\" modification history
.\" --------------------
.\" 01a,22aug03,scm  correct TE pairing...
.\" 01a,27Aug02,vgd  created, derived from ibrh80200
.\"
.TH ixdp2400_be T "Intel IXDP240_be" "Rev: 01 Aug 02" "TORNADO REFERENCE: VXWORKS"

.SH "NAME"
.aX "Intel IXDP2400_be"


.SH "INTRODUCTION"
This manual entry provides board-specific information necessary to run
VxWorks for the IXDP2400_be BSP.  The ixdp2400_be BSP release requires an
Intel IXDP2400 refernce platform board.  Before using a board with VxWorks,
verify that the board runs in the factory configuration using vendor-supplied 
firmware and jumper settings, and checking the RS-232 and Ethernet connections.  

The ixdp2400_be BSP is based around the Intel ixp2400 network Processor unit.  This
board is composed of dual Intel ixp2400 processors (XScale)units arranged in a 
pipelined ingress-egress fashion for optimum performance of full duplex OC-48 data 
through put rates. The Egress NPU is configured as Master NPU and the Ingress as Slave NPU.
Each NPU block consists of the following

ixdp2400 NPU block Specification:
.CS
Processor:             Dual INTEL IXP2400,600MHz
Memory,
  SDRAM:               512 Mbytes (up to 2GB future), 150MHz/300MT 
  QDR SRAM:            16MB QDR SRAM on Channel 1 for each NPU @ 200MHz/400MT w/ 4 soldered down parts
                       16MB QDR SRAM on Channel 2 for Egress NPU @ 200MHz/400MT w/ 4 soldered down parts
                       Ingress NPU Channel 2 is modular @ 100MHz/200MT w/ support for a TCAM module. 
  FLASH:               16Mbyte , (100-150nS??)
I/O,
  Ethernet -1 Port per NPU:   10/100BaseT (82559ER based)
  Serial   -1 Port per NPU:   RS232, 115.2K (TX,RX,CTS,RTS), 9-Pin 'D'(??)
PCI:                          64-bit, 66MHz, (3.3V?), Bus version 2.2 
Power Delivery Subsystem:
                       AC/DC power module to supply 2.5V, 3.3V, 5.0V and 12V
                       Regulated DC/DC power modules to step down 3.3V to 0.75V, 1.25V, 1.3V, 1.5V, 1.8V
Debug Support:         Jtag-ICE connector, Netrom Connector
Other:                 4 char LCD display panel
.CE


.SS "ixdp2400_be BSP DETAILS"
.SS "Boot ROMs"
The default boot image provided with this BSP includes a
mechanism for loading a standard VxWorks image over Ethernet.

The bootrom image has been tested running from flash.

.CS
  make bootrom.hex
.CE

This builds the file 'bootrom.hex' which can be burned into flash using
a dedicated flash burner or by using visionClick.

The board uses this image to boot and load VxWorks images developed
from the BSP over the network.

.IP "1)"
Configure the visionCLICK project:
In the 'Welcome To visionCLICK' window, click on the 'Configure' button,
this invokes the 'PROJECTS/LOAD' window.  In this window, click the '+'
left to '[e-mail]'.  This displays the project 
configuration.
Right-click the 'Microprocessors' option and choose your CPU type, for
example: 'XSCALE->IXP2400'.  Verify that the 'Target Control' option
points to 'visionPROBE' for visionPROBE I/II or 'visionICE' for visionICE
I/II.  Also, click the 'Communications' tab and verify that the
'Normal Port/Rate' and 'Download Port/Rate' are accurate for your 
connection,
for example: 'LPT1'  for visionPROBE II.  Click the 'Save' button at the
bottom of the window, then click the 'Activate' button.

.IP "2)"
Make sure SW2701 and SW2702 are set up for the proper Ice JTAG settings
you wish to work with.

Get into Background Mode:

Execute the 'IN' command to reset the board and initialize it with the
register setting.

.IP "3)"
Generating the visionCLICK compatible flash image:
In visionCLICK, select 'Convert Object Modules' from the Tools pull-down
menu.  This invokes the 'CONVERT BINARY AND SYMBOL OBJs' window:
        1. In the 'Select Input Object Module to Convert' slot, enter the
        full path of, or browse to, the 'bootrom.hex' image.

        2. Check the 'Create Flat BIN File For Flash Programming' box.

        3. Set the 'Range Of' field to 0x0, and the 'Range To' field
        to 0x00800000. This allows up to a 8 MB image to be processed. 
Larger
        images require an equivalently larger 'Range To' value.

        4. Click the 'Convert' button to initiate the conversion.

        5. The 'bootrom.bin' image will be generated in the same location
        as the source 'bootrom.hex' image.

.IP "4)"
Programming the ixdp2400 flash:
In visionCLICK, select 'Program Flash Devices' from the Tools pull-down
menu.  This invokes the 'TF FLASH PROGRAMMING' window:

        1. In the 'Flash Card or PC Host File Name and Path' group,
        enter the full path to the location of the bootrom.bin in the 
edit box,
        or use the 'Select' button to browse to the file location.  Make 
sure
        the 'Bias' address is 0 by entering 0 in the
        '+/- Bias' edit box in the 'CHOOSE A FILE FROM HOST PC' dialog box.

        2. In the 'Programming Algorithm' group, in the edit box, click the
        'Select' button and select the following flash device:

        For the 16 MB on-board flash: 'INTEL  28F128Jx (16384 x 8)  1 
Device'

        3. Set the base address of the flash to 00000000, check the 
'Erase to 0x'
        radio button setting the 'Erase to' value to ffffff. This allows 
for a
        8 MB image. Larger images require an equivalently larger 'Erase 
to' value.

        4. Set the 'Available RAM Workspace' setting to 10000000. Set the
        'Bytes Of Target RAM Required' to 26704.

        5. Press the 'Erase Only' button.  Wait until the 'Done' 
response appears
        in the visionClick Terminal window.

        6. Press the 'Program Only' button. This process can take a
        few minutes. The process is complete when the 'OK' prompt appears.

.IP "5)"
Running the VxWorks Boot ROM program:
The flash memory is now programmed with the new boot program.  To execute
the new boot program, turn the board off and on. Make sure SW2701 and SW2702
are set for normal operation.

.SS "ROM Considerations"
The IXDP2400 will be delivered with two Flashes soldered one for each of the NPUs. 
To build the bootRom images see the manual entry for "Make Targets"

To use bebug the image with visionCLICK and visionPROBE II, you must use the
visionClick documentation.

The new 'bootrom' file must be converted to the proper format using the
instructions provided in 'Creating the proper vxWorks.ab, bootrom.abg,
and bootrom.bin to run under visionClick' below. 

.SS "Creating the proper vxWorks.bdx, bootrom.bdx, and bootrom.bin to run under visionClick"
In order to use visionClick/visionProbe, you must convert the standard boot
ROM and VxWorks images generated via the makefile to the proper format for
visionClick. To generate the proper format, complete the following steps:

.IP "1)"
Under your local 'estii' directory run the 'objcvt' utility on your VxWorks
image to produce a vxWorks.ab file for visionClick.
( <command prompt> ..\..\estii\objcvt vxWorks )
.IP "2)"
Under your local 'estii' directory run the 'objcvt' utility on your boot
ROM image to produce a bootrom.ab image for visionClick.
( <command prompt> ..\..\estii\objcvt bootrom )
.IP "3)"
.LP


.SS "Make Targets"
bootrom and vxWorks, vxWorks.st, vxWorks_rom and vxWorks.st_rom  have been tested.


.SS "Libraries"
This BSP release requires three directories which contain object
files for the XScale microarchitecture:
.CS
    Little Endian
    -------------
    objXSCALEgnuvx
    objXSCALEgnuvxwv
    objXSCALEgnutest

    Big Endian
    -------------
    objXSCALEgnubevx
    objXSCALEgnubevxwv
    objXSCALEgnubetest
.CE

These object files are built into the following architecture libraries:
.CS
    Little Endian
    -------------
    target/lib/libXSCALEgnuvx.a
    target/lib/libXSCALEgnuwv.a
    target/lib/libXSCALEgnugcc.a
    target/lib/libXSCALEgnutest.a

    Big Endian
    -------------
    target/lib/libXSCALEgnubevx.a
    target/lib/libXSCALEgnubewv.a
    target/lib/libXSCALEgnubegcc.a
    target/lib/libXSCALEgnubetest.a
.CE

These files, along with the BSP, are used to construct a VxWorks image
designed to run on the ixdp2400 Platform board.  Please refer to the
.I "Tornado BSP Developer's Kit for VxWorks User's Guide"
for more information on building the various VxWorks images.

.SS "Flash memory as NVRAM"
If the BSP is configured with INCLUDE_FLASH defined, standard VxWorks
flash support is included.

The following information may be required (depending on your boot method) for
storage in flash:

        boot device
        unit number
        processor number
        host name
        file name
        inet on ethernet (e)
        host inet (h)
        gateway inet (g)
        user (u)
        ftp password (pw)
        flags (f)
        target name (tn)

Please refer to the
.I "Tornado User's Guide"
for more information on booting VxWorks.


.SS "ixp2400 Memory Map"
.CS
Address range           Size   Resource
-------------           ----   --------
0xE0000000-0xFFFFFFFF   512M   PCI MEMORY
0xDF000000-0xDFFFFFFF    32M   PCI Controller CSRs
0xDE000000-0xDDFFFFFF    32M   PCI config Registers
0xDC000000-0xDEFFFFFF    32M   PCI spec/IACK
0xDA000000-0xDBFFFFFF    32M   PCI Config
0xD8000000-0xD9FFFFFF    32M   PCI I/O
0xD6000000-0xD7FFFFFF    32M   Xscale Local CSRs
0xD2000000-0xD5FFFFFF    64M   Reserved
0xD0000000-0xD1FFFFFF    32M   DDR CSRs
0xCC000000-0xCFFFFFFF    64M   SRAM CSRs and Queue Array
0xCA000000-0xCBFFFFFF    32M   Scratch
0xC8000000-0xC9fFFFFF    32M   MSF
0xC4000000-0xc7fFFFFF    64M   SlowPort
0xC2000000-0xC3ffFFFF    32M   Reserved
0xC0000000-0xC1fFFFFF    32M   CAP CSRs
0x80000000-0xBffFFFFF    1GB   QDR SRAM
0x20000000-0x7ffFFFFF    1.5GB Reserved (FUTURESDRAM Expansion)
0x00000000-0x1fffffff    512M  DDR SDRAM
.CE


.SS "Serial Configuration"
There is only one serial port (per NPU) on the IXDP2400 Platform board.
Each port will use a 6-pin stacked RJ11 connector, which will be located 
at the front panel of the IXDP2400 platform baseboard. The ADM3203 RS232 line drivers 
from Analog Devices are used to provide the appropriate voltage levels to 
support RS232 signaling. 
The default configuration is 38400 baud, 8 data bits, no parity, 1 stop
bit.  This connector is located in front of the board (see "BOARD LAYOUT").
The left side port is for the Master/Egress NPU and right side port is for 
the Ingress/Slave NPU.  The port is "data leads only", that is, there are 
no handshake lines provided at all. 

The ports will have a pin out as follows:
.CS 
pin1 - Shield
pin2 - RXD
pin3 - TXD
pin4 - GND
pin5 - GND
pin6 - GND
.CE


.SS "SCSI Configuration"
The ixdp2400 platform board does not have any on-card SCSI devices.
This BSP does not support SCSI.


.SS "Network Configuration"
Each NPU will have a 10/100BaseT Ethernet debug MAC which will be implemented on the
secondary PCI interface of the 21154 PCI-PCI bridge. Two 82559ER Ethernet MACs will 
be used for this implementation. The 82559ER is Intel's fully integrated 
10BASE-T/100BASE-TX LAN solution.

Two LEDs are provided on the RJ-45 connector.  The first indicates the link status 
and activity.  This LED is illuminated (solid green) when link pulses are received 
and no other activity is present.  The LED flashes when a valid link exists and data 
is being received or transmitted.  The 2nd LED indicates the link speed as determined 
during auto-negotiation (or link pulse inspection).  The indicator lights solid Yellow for 
100Mbit operation ans solid green for 10Mbit operation. 


.SS "VME Access"
The ixdp2400 platform bseboard does not have VME bus support.


.SS "PCI Access" 
IXDP2400 has 2 PCI bus. On primary bus it has two IXP2400 (one master and one slave),
21555 (non-transparent PCI to PCI bridge) and 21154 (transparent PCI to PCI bridge). 
On secondary bus it has two 82559 and one PMC connector.The maximum PCI devices 
supported on the IXDP2400 is 8. Here are the device and bus nos. for different
PCI device:
Bus 0:
Device 4 - 21154
Device 5 - Slave IXP2400
Device 6 - 21555
Device 7 - Master IXP2400

Bus 1:
Device 3 - Slave's 82559
Device 4 - Master's 82559
Device 7 - PMC connector


.SS "BOOT DEVICES"
The supported boot device is:

        'fei0 - 10/100BaseT Ethernet

.SH "SPECIAL CONSIDERATIONS"

.SS "Cache/MMU considerations"
The ixdp2400 extends the page attributes defined by the C & B bits in
the page descriptors with an additional X bit.  This bit allows additional
attributes to be encoded when X=1.  To gain access to the X bit the ixdp2400
BSP has been modified to support Extended Small Page Tables.  The X bit is
the LSB of the TEX (type extension) field.

If the X bit for a descriptor is zero, the C & B bits operate as mandated
by the ARM architecture.  It the X bit for a descriptor is one, the C & B
bits meanings are extended.

With this support the following state flags have been added:

VM_STATE_CACHEABLE_MINICACHE - cache policy is determined by MD field
                               of Auxiliary Control register

VM_STATE_EX_CACHEABLE        - write back, read/write allocate
VM_STATE_EX_CACHEABLE_NOT
VM_STATE_MASK_EX_CACHEABLE

VM_STATE_EX_BUFFERABLE       - writes will not coalesce into buffers
VM_STATE_EX_BUFFERABLE_NOT
VM_STATE_MASK_EX_BUFFERABLE

With the state VM_STATE_CACHEABLE_MINICACHE set, pages set to this state
using vmStateSet() will result in those pages being cached in the
mini-cache, and not in the main data cache.

Calling cacheInvalidate(DATA_CACHE, ENTIRE_CACHE) will also invalidate the
mini-cache, but in all other aspects, no support is provided for
the mini-cache, and the user is entirely responsible for ensuring
cache coherency.

Please consult the Intel XScale Core Developer's Manual for more
information on the extended page table and X bit support.

Each NPU on the IXDP2400 Development Platform BaseBoard has 512MB of SDRAM.
Out of which 32 MB. The lower 480 MB of memory is made non-cacheable 
and non bufferable is reserved for use by the Application/Micro Engines. 
The upper 32 MB of memmory is mapped to virtual 0x0 and is used by VxWorks.
In order for the mmuLib/cacheLib code to support this, the BSP has to 
provide routines to map between virtual and physical addresses.
See the man entries for the BSP routines sysVirtToPhys() and sysPhysToVirt() 
for details.In order for the mmuLib/cacheLib code to support this, the BSP has to 
provide routines to map between virtual and physical addresses.  See the man entries 
for the BSP routinessysVirtToPhys() and sysPhysToVirt() for details.

The default mapping remaps the upper 32 MB of SDRAM to virtual
address 0, so that the exception vectors lie in RAM.  This then
requires the lower 480 MB of SDRAM to be  remapped to a higher address.
Because a large amount of SDRAM is to be used by the MicroEngines 
for packet data, and because this data must be non-cacheable 
when accessed by the XScale core, the lower part of
SDRAM is mapped in a separate virtual memory, and this range
is marked as non-cacheable.