ixdp2400pci.c

ixp2400 bsp for vxworks

/* ixp2400Pci.c - Intel IXP2400 PCI Unit driver */

/* Copyright 1998 Wind River Systems, Inc.; Copyright 1999 Intel Corp. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01b,15jan03,scm  correct var declarations to support serial only mode...
01a,25mar02,lagarwal  created from ixp1200eb_be
*/

/*
DESCRIPTION
This device driver code for the Intel IXP2400 PCI unit.

It the function sysPciInit(), which should be called from
sysHwInit() to initialize the PCI unit on the IXP2400.

It also contains the function sysPciAssignAddrs() which will 
examine PCI space and program ourself and all other PCI devices
dynamically, based on how much addresses space each device needs.

*/

#include "vxWorks.h"
#include "config.h"
#include "ixdp2400.h"
#include "ixdp2400Pci.h"
#include "ixdp2400I2c.h"
#include "ixdp2400Misc.h"
#ifdef AUTO_PCI_CONFIG
#ifdef INCLUDE_AUTO_PCI_CONFIG_SHOW_ROUTINE
#include <stdio.h>
#endif
#endif
#include "taskLib.h"

extern void singleFlashBootLow(void);
extern void singleFlashBootHi(void);

extern UINT32 strapOptionsVal;
extern struct board_config *pBoardCfgData;
extern int sysStartType;
extern UINT32 vxWorksTextAddr;
IMPORT int pciLibInitStatus;

IMPORT void	romInit ();
UINT32 slaveBootStart;
UINT32 ramCopyAdrs;

PciDevice *pSlave;

/* local defines  */

#ifdef AUTO_PCI_CONFIG
#define MAX_DEVICES 16

#ifndef INITIAL_PCI_CMD
#define INITIAL_PCI_CMD PCI_CMD_IO_ENABLE
#endif
#endif /* ifdef AUTO_PCI_CONFIG */

/* locals */

#ifdef AUTO_PCI_CONFIG

static PciDevice devices[MAX_DEVICES];
static int nDevices;
static int tbBusNo, tbDeviceNo, tbFuncNo;

#endif /* ifdef AUTO_PCI_CONFIG */

/* function prototypes */

void sysPciAssignAddrs(void);

/******************************************************************************
*
* void slaveNPUISR(void)
*
* This routine is interrupt service routine for slave NPU interrupt.
* This function can only be called on master NPU.
*
* RETURNS: nothing
*/
void slaveNPUISR(void)
{
	int mailBoxVal = 0;
	int temp;
	int csrBarAddr;

	/* check for master */
	if(!isNPUMaster())
	{
		return;
	}

	csrBarAddr = pSlave->bar[CSR_BAR].address + CPU_PCI_MEM_ADRS;
	*(UINT32 *)(IXP2400_PCI_CONTROL) |= (IXP2400_PCI_CONTROL_BE_DEO |
			IXP2400_PCI_CONTROL_BE_DEI | IXP2400_PCI_CONTROL_BE_BEO |
			IXP2400_PCI_CONTROL_BE_BEI);
	*((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL)) |=
				(IXP2400_PCI_CONTROL_BE_DEO | IXP2400_PCI_CONTROL_BE_DEI |
				IXP2400_PCI_CONTROL_BE_BEO | IXP2400_PCI_CONTROL_BE_BEI);
	temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL));

	/* turn off the interrupt */
	*((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL)) &= ~(1 << 24);

	/* check the mailbox register to find out the cause for interrupt */
	IXP2400_REG_READ((csrBarAddr + SLAVE_MAILBOX_0), mailBoxVal);

	*((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL)) &=
		~(IXP2400_PCI_CONTROL_BE_DEO | IXP2400_PCI_CONTROL_BE_DEI | IXP2400_PCI_CONTROL_BE_BEO
		| IXP2400_PCI_CONTROL_BE_BEI);
	temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL));
	*(UINT32 *)(IXP2400_PCI_CONTROL) &= ~(IXP2400_PCI_CONTROL_BE_DEO |
		IXP2400_PCI_CONTROL_BE_DEI | IXP2400_PCI_CONTROL_BE_BEO | IXP2400_PCI_CONTROL_BE_BEI);

	switch(mailBoxVal)
	{
	case 1:
		/* reset everything */
		*((volatile UINT32 *)IXP2400_RESET_0) |= (1 << 16);
		break;
	case 2:
		sysToMonitor(BOOT_NO_AUTOBOOT);
		break;
	default:
		break;
	}
	return;
}

/*******************************************************************************
*
* sysInitSlave - This function initializes the slave NPU.
*
* RETURNS: None.
*/

void sysInitSlave(void)
{
	int i;
	int temp;
	int slaveSdramPassed = 1;
	int csrBarAddr;
	int dramBarAddr;
    FAST int locKey;

    locKey = intLock ();

	/* search for slave */
	if((pSlave = pciDeviceGet(IXP2400_VENDOR_ID, IXP2400_DEVICE_ID, 0)) == NULL)
		return;

	csrBarAddr = pSlave->bar[CSR_BAR].address + CPU_PCI_MEM_ADRS;
	dramBarAddr = pSlave->bar[SD_BAR].address;

	/* PCI unit does a byte swapping by default.
	but we don't want to swap bytes when copying into slave's memory.
	So set these bits so that PCI unit doesn't do byte swapping. */
	*(UINT32 *)(IXP2400_PCI_CONTROL) |= (IXP2400_PCI_CONTROL_BE_DEO |
			IXP2400_PCI_CONTROL_BE_DEI | IXP2400_PCI_CONTROL_BE_BEO |
			IXP2400_PCI_CONTROL_BE_BEI);
	*((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL)) |=
				(IXP2400_PCI_CONTROL_BE_DEO | IXP2400_PCI_CONTROL_BE_DEI |
				IXP2400_PCI_CONTROL_BE_BEO | IXP2400_PCI_CONTROL_BE_BEI);
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_CONTROL));
#endif

	if((*(UINT32 *)(csrBarAddr + SLAVE_STRAP_OPTIONS) & CFG_PROM_BOOT))
	{
		/* slave has flash */
	}
	else
	{
		/* slave doesn't have flash */
		/* initialize slave */

		/* silicon bug work around */
		/* set the latency timer value to max */
		pciConfigOutByte(pSlave->bus, pSlave->device, pSlave->func, PCI_CFG_LATENCY_TIMER,
			(0x1F << 3));
		/* enable outbound pci int. from xscale */
		*((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_OUT_INT_MASK)) &= XSIM;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_OUT_INT_MASK));
#endif			
		/* set the upper bits for pci mem and io transactions */
		IXP2400_REG_WRITE((csrBarAddr + SLAVE_PCI_ADDR_EXT), 0);
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_PCI_ADDR_EXT));
#endif
		/* slave pci init is complete. So start accepting pci transactions */
		*((volatile UINT32 *)(csrBarAddr + SLAVE_IXP_RESET0)) |= INIT_COMP;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_IXP_RESET0));
#endif			
		/* now I need to config SDRAM/SRAM also. So, that I can download image in SDRAM.
		setup operating freq. for SDRAM/SRAM interface */
		IXP2400_REG_WRITE((csrBarAddr + SLAVE_DU_RCOMP_IO_CONFIG),
			DDR_RCOMP_IO_CONFIG_VAL);
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_DU_RCOMP_IO_CONFIG));
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_CCR));
		temp &= ~(0xF00FF);
        if(ixp2400XtalFreq == 50000000)
		{
			temp |= ((SDRAM_DIVISOR << 16) | (SRAM_150MHZ_DIVISOR << 4) | SRAM_150MHZ_DIVISOR);
		}
		else
		{
			temp |= ((SDRAM_DIVISOR << 16) | (SRAM_200MHZ_DIVISOR << 4) | SRAM_200MHZ_DIVISOR);
		}
#else
		temp = *((volatile UINT32 *)IXP2400_CLOCK_CONTROL);
#endif

		*((volatile UINT32 *)(csrBarAddr + SLAVE_CCR)) = temp;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_CCR));
#endif
        delayUSec(1000);

		/* now config SDRAM interface */
		IXP2400_REG_WRITE((csrBarAddr + SLAVE_DU_RDDLYSEL_RECEN),
			DDR_RDDLYSEL_RECEN_VAL);
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_DU_RDDLYSEL_RECEN));
#endif
		IXP2400_REG_WRITE((csrBarAddr + SLAVE_DU_RX_DLL),
			DDR_RX_DLL_VAL);
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_DU_RX_DLL));
#endif
		IXP2400_REG_WRITE((csrBarAddr + SLAVE_DU_RX_DESKEW), DDR_RX_DESKEW_VAL);
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + SLAVE_DU_RX_DESKEW));
#endif









	/* cr0_dstrengthsel*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DSTRENGTHSEL_FRM_PCI)) = 0x036db6db;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DSTRENGTHSEL_FRM_PCI));
#endif

	/* cr0_ddqrcomp*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DDQRCOMP_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DDQRCOMP_FRM_PCI));
#endif

	/* cr0_dctlrcomp*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DCTLRCOMP_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DCTLRCOMP_FRM_PCI));
#endif

	/* cr0_drcvrcomp*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DRCVRCOMP_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DRCVRCOMP_FRM_PCI));
#endif

	/* cr0_dckercomp*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DCKERCOMP_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DCKERCOMP_FRM_PCI));
#endif

	/* cr0_dcsrcomp*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DCSRCOMP_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DCSRCOMP_FRM_PCI));
#endif

	/* cr0_dckrcomp*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DCKRCOMP_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DCKRCOMP_FRM_PCI));
#endif

	/* cr0_dx8x16ckecscksel*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DX8X16CKECSCKSEL_FRM_PCI)) = 0x11111111;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DX8X16CKECSCKSEL_FRM_PCI));
#endif

	/* cr0_rcompprd*/
	*((volatile UINT32 *)(csrBarAddr + CR0_RCOMPPRD_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_RCOMPPRD_FRM_PCI));
#endif

	/* cr0_digfil*/
	*((volatile UINT32 *)(csrBarAddr + CR0_DIGFIL_FRM_PCI)) = 0;
#if A0_REV
	temp = *((volatile UINT32 *)(csrBarAddr + CR0_DIGFIL_FRM_PCI));
#endif

	/* Program DDR DQ/DQS pull-up and pull-down Slew Lookup table registers */
	/* (cr0_ddqpslew0 - cr0_ddqpslew3) and (cr0_ddqnslew0 - cr0_ddqnslew3) */
	for(i = (SLAVE_DRAM_CH0_BASE + 0x150); i <= (SLAVE_DRAM_CH0_BASE + 0x188); i += 8)
	{
		*((volatile UINT32 *)(csrBarAddr + i)) = 0xcccccccc;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + i));
#endif
	}

	/* Program MA/BA/RAS#/CAS#/WE# pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dctlpslew0 - cr0_dctlpslew3) and (cr0_dctlnslew0 - cr0_dctlnslew3) */
	for(i = (SLAVE_DRAM_CH0_BASE + 0x198); i <= (SLAVE_DRAM_CH0_BASE + 0x1D0); i += 8)
	{
		*((volatile UINT32 *)(csrBarAddr + i)) = 0xcccccccc;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + i));
#endif
	}

	/* Program RCV pull-up and pull-down Slew Lookup table registers */
	/* (cr0_drcvpslew0 - cr0_drcvpslew3) and (cr0_drcvnslew0 - cr0_drcvnslew3) */
	for(i = (SLAVE_DRAM_CH0_BASE + 0x1E0); i <= (SLAVE_DRAM_CH0_BASE + 0x218); i += 8)
	{
		*((volatile UINT32 *)(csrBarAddr + i)) = 0xcccccccc;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + i));
#endif
	}

	/* Program CKE x8 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dckex8pslew0 - cr0_dckex8pslew3) and (cr0_dckex8nslew0 - cr0_dckex8nslew3) */
	for(i = (SLAVE_DRAM_CH0_BASE + 0x230); i <= (SLAVE_DRAM_CH0_BASE + 0x268); i += 8)
	{
		*((volatile UINT32 *)(csrBarAddr + i)) = 0xcccccccc;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + i));
#endif
	}

	/* Program CKE x16 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dckex16pslew0 - cr0_dckex16pslew3) and (cr0_dckex16nslew0 - cr0_dckex16nslew3) */
	for(i = (SLAVE_DRAM_CH0_BASE + 0x270); i <= (SLAVE_DRAM_CH0_BASE + 0x2A8); i += 8)
	{
		*((volatile UINT32 *)(csrBarAddr + i)) = 0xcccccccc;
#if A0_REV
		temp = *((volatile UINT32 *)(csrBarAddr + i));
#endif
	}

	/* Program CS# x8 pull-up and pull-down Slew Lookup table registers */
	/* (cr0_dcsx8pslew0 - cr0_dcsx8pslew3) and (cr0_dcsx8nslew0 - cr0_dcsx8nslew3) */
	for(i = (SLAVE_DRAM_CH0_BASE + 0x2B8); i <= (SLAVE_DRAM_CH0_BASE + 0x2F0); i += 8)
	{
		*((volatile UINT32 *)(csrBarAddr + i)) = 0xcccccccc;
#if A0_REV