📄 transmitter.v
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module uart1(clk, rst_n, start, inbyte, outdate);
input clk, rst_n, start;
input [7:0] inbyte;
output outdate;
reg outdate;
reg [7:0] store;
reg [3:0] counter;
reg [3:0] st, next_st;
parameter st_0 = 0, st_1 = 1, st_2 = 2, st_3 = 3, st_4 = 4,
st_5 = 5, st_6 = 6, st_7 = 7, st_8 = 8, st_9 = 9, st_10 = 10, st_11 = 11, st_12 = 12, st_13 = 13;
////////////////////////////////////////
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 0)
st <= st_0;
else
st <= next_st;
end
////////////////////////////////////////
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 0)
next_st <= st_0;
else
begin
case(st)
st_0:
begin
if(start == 1)
begin
counter <= 0;
store <= inbyte;
next_st <= st_1;
end
else
next_st <= st_0;
end
st_1:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_2;
end
else
begin
counter <= counter + 1;
next_st <= st_1;
end
end
st_2:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_3;
end
else
begin
counter <= counter + 1;
next_st <= st_2;
end
end
st_3:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_4;
end
else
begin
counter <= counter + 1;
next_st <= st_3;
end
end
st_4:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_5;
end
else
begin
counter <= counter + 1;
next_st <= st_4;
end
end
st_5:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_6;
end
else
begin
counter <= counter + 1;
next_st <= st_5;
end
end
st_6:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_7;
end
else
begin
counter <= counter + 1;
next_st <= st_6;
end
end
st_7:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_8;
end
else
begin
counter <= counter + 1;
next_st <= st_7;
end
end
st_8:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_9;
end
else
begin
counter <= counter + 1;
next_st <= st_8;
end
end
st_9:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_10;
end
else
begin
counter <= counter + 1;
next_st <= st_9;
end
end
st_10:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_11;
end
else
begin
counter <= counter + 1;
next_st <= st_10;
end
end
st_11:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_12;
end
else
begin
counter <= counter + 1;
next_st <= st_11;
end
end
st_12:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_13;
end
else
begin
counter <= counter + 1;
next_st <= st_12;
end
end
st_13:
begin
if(counter == 15)
begin
counter <= 0;
next_st <= st_0;
end
else
begin
counter <= counter + 1;
next_st <= st_13;
end
end
default:
next_st <= st_0;
endcase
end
end
/////////////////////////////////////////////////
always@(rst_n or st)
begin
if(rst_n == 0)
outdate <= 1;
else
case(st)
st_0:
outdate <= 1;
st_1:
outdate <= 0;
st_2:
outdate <= 0;
st_3:
outdate <= store[7];
st_4:
outdate <= store[6];
st_5:
outdate <= store[5];
st_6:
outdate <= store[4];
st_7:
outdate <= store[3];
st_8:
outdate <= store[2];
st_9:
outdate <= store[1];
st_10:
outdate <= store[0];
st_11:
outdate <= (store[7] + store[6] + store[5] + store[4] + store[3] + store[2] + store[1] + store[0])%2;
st_12:
outdate <= 0;
st_13:
outdate <= 0;
default:
outdate <= 1;
endcase
end
///////////////////////////////////////////////
endmodule
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