hdpdeps.ref

CPU 设计

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FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/CPU_16.vhdl 2007/11/12.17:58:42
FL $XILINX/bin/CPU_16/CPU_16.vhdl 2007/11/18.19:43:12
FL $XILINX/bin/CPU_16/ALU.vhdl 2007/11/18.20:10:58
FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/write_back_control.vhdl 2007/11/16.21:53:59
FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/code_control.vhdl 2007/11/10.15:24:50
FL F:/cpu6/cpu6/ALU.vhdl 2007/11/18.20:10:58
EN work/ALU             FL F:/cpu6/cpu6/ALU.vhdl PH unisim/VCOMPONENTS \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/ALU/BEHAVIORAL  FL F:/cpu6/cpu6/ALU.vhdl EN work/ALU
FL $XILINX/bin/cpu6/cpu6/ALU.vhdl 2007/11/18.20:10:58
FL $XILINX/bin/CPU_16/code_control.vhdl 2007/11/19.17:54:58
FL $XILINX/bin/cpu6/cpu6/CPU_16.vhdl 2007/11/18.19:43:12
FL F:/cpu6/cpu6/write_back_control.vhdl 2007/11/18.18:35:24
EN work/WRITE_BACK_CONTROL FL F:/cpu6/cpu6/write_back_control.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH unisim/VCOMPONENTS
AR work/WRITE_BACK_CONTROL/BEHAVIORAL FL F:/cpu6/cpu6/write_back_control.vhdl \
      EN work/WRITE_BACK_CONTROL
FL F:/cpu6/cpu6/memery_control.vhdl 2007/11/17.11:01:54
EN work/MEMERY_CONTROL  FL F:/cpu6/cpu6/memery_control.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/MEMERY_CONTROL/BEHAVIORAL FL F:/cpu6/cpu6/memery_control.vhdl \
      EN work/MEMERY_CONTROL
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/CPU_16.vhdl 2007/11/18.19:43:10
FL $XILINX/bin/CPU_16/visit_memery_control.vhdl 2007/11/17.10:41:22
FL F:/cpu6/cpu6/visit_memery_control.vhdl 2007/11/17.10:41:22
EN work/VISIT_MEMERY_CONTROL FL F:/cpu6/cpu6/visit_memery_control.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH unisim/VCOMPONENTS
AR work/VISIT_MEMERY_CONTROL/BEHAVIORAL FL F:/cpu6/cpu6/visit_memery_control.vhdl \
      EN work/VISIT_MEMERY_CONTROL
FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/clock_control.vhdl 2007/11/16.20:43:15
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/memery_control.vhdl 2007/11/17.11:01:52
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/code_control.vhdl 2007/11/18.19:56:22
FL $XILINX/bin/CPU_16/write_back_control.vhdl 2007/11/18.18:35:24
FL $XILINX/bin/cpu6/cpu6/write_back_control.vhdl 2007/11/18.18:35:24
FL $XILINX/bin/CPU_16/memery_control.vhdl 2007/11/17.11:01:54
FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/ALU.vhdl 2007/11/16.23:28:26
FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/visit_memery_control.vhdl 2007/11/16.21:26:53
FL $XILINX/bin/cpu6/cpu6/clock_control.vhdl 2007/11/17.10:41:28
FL e:/资料/计算机设计与实践/cpu_16/cpu_16/cpu_16/memery_control.vhdl 2007/11/17.10:16:39
FL F:/cpu6/cpu6/code_control.vhdl 2007/11/19.17:54:58
EN work/CODE_CONTROL    FL F:/cpu6/cpu6/code_control.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED PH unisim/VCOMPONENTS
AR work/CODE_CONTROL/BEHAVIORAL FL F:/cpu6/cpu6/code_control.vhdl \
      EN work/CODE_CONTROL
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/write_back_control.vhdl 2007/11/18.18:35:23
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/clock_control.vhdl 2007/11/17.10:41:26
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/visit_memery_control.vhdl 2007/11/17.10:41:21
FL $XILINX/bin/cpu6/cpu6/code_control.vhdl 2007/11/19.17:54:58
FL $XILINX/bin/cpu6/cpu6/visit_memery_control.vhdl 2007/11/17.10:41:22
FL E:/资料/计算机设计与实践/CPU_16/CPU_16/CPU_16/ALU.vhdl 2007/11/18.20:10:57
FL $XILINX/bin/cpu6/cpu6/memery_control.vhdl 2007/11/17.11:01:54
FL F:/cpu6/cpu6/CPU_16.vhdl 2007/11/18.19:43:12
EN work/CPU_16          FL F:/cpu6/cpu6/CPU_16.vhdl PB ieee/STD_LOGIC_1164 \
      PH unisim/VCOMPONENTS
AR work/CPU_16/BEHAVIORAL FL F:/cpu6/cpu6/CPU_16.vhdl EN work/CPU_16 CP BUFGP \
      CP ALU            CP CLOCK_CONTROL  CP CODE_CONTROL   CP MEMERY_CONTROL \
      CP VISIT_MEMERY_CONTROL CP WRITE_BACK_CONTROL
FL F:/cpu6/cpu6/clock_control.vhdl 2007/11/17.10:41:28
EN work/CLOCK_CONTROL   FL F:/cpu6/cpu6/clock_control.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PH unisim/VCOMPONENTS
AR work/CLOCK_CONTROL/BEHAVIORAL FL F:/cpu6/cpu6/clock_control.vhdl \
      EN work/CLOCK_CONTROL
FL $XILINX/bin/CPU_16/clock_control.vhdl 2007/11/17.10:41:28