hdllib.ref

CPU 设计

AR write_back_control behavioral F:/cpu6/cpu6/write_back_control.vhdl sub00/vhpl13
AR code_control behavioral C:/Xilinx/bin/cpu6/cpu6/code_control.vhdl sub00/vhpl07
EN write_back_control NULL C:/Xilinx/bin/cpu6/cpu6/write_back_control.vhdl sub00/vhpl12
AR visit_memery_control behavioral F:/cpu6/cpu6/visit_memery_control.vhdl sub00/vhpl11
EN memery_control NULL C:/Xilinx/bin/cpu6/cpu6/memery_control.vhdl sub00/vhpl08
AR alu behavioral F:/cpu6/cpu6/ALU.vhdl sub00/vhpl03
EN code_control NULL C:/Xilinx/bin/cpu6/cpu6/code_control.vhdl sub00/vhpl06
EN cpu_16 NULL F:/cpu6/cpu6/CPU_16.vhdl sub00/vhpl00
AR clock_control behavioral F:/cpu6/cpu6/clock_control.vhdl sub00/vhpl15
EN visit_memery_control NULL F:/cpu6/cpu6/visit_memery_control.vhdl sub00/vhpl17
EN clock_control NULL F:/cpu6/cpu6/clock_control.vhdl sub00/vhpl14
AR memery_control behavioral C:/Xilinx/bin/cpu6/cpu6/memery_control.vhdl sub00/vhpl16
AR cpu_16 behavioral F:/cpu6/cpu6/CPU_16.vhdl sub00/vhpl01
EN alu NULL F:/cpu6/cpu6/ALU.vhdl sub00/vhpl18