hdpdeps.ref

CPU 设计

V1 56
FL E:/资料/计算机设计与实践/MyCPU16/write_back.vhdl 2007/11/10.16:41:03
FL $XILINX/bin/MyCPU16/visit_memory.vhdl 2007/11/10.16:54:52
FL F:/MyCPU16/code.vhdl 2007/11/22.17:49:48
EN work/CODE            FL F:/MyCPU16/code.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED PH unisim/VCOMPONENTS
AR work/CODE/BEHAVIORAL FL F:/MyCPU16/code.vhdl EN work/CODE CP BUFGP
FL e:/资料/计算机设计与实践/mycpu16/clock.vhdl 2007/11/10.16:28:45
FL F:/MyCPU16/memory.vhdl 2007/11/10.16:29:22
FL F:/MyCPU16/ALU.vhdl 2007/11/22.17:49:42
EN work/ALU             FL F:/MyCPU16/ALU.vhdl PH unisim/VCOMPONENTS \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/ALU/BEHAVIORAL  FL F:/MyCPU16/ALU.vhdl EN work/ALU  CP BUFGP
FL e:/资料/计算机设计与实践/mycpu16/memory.vhdl 2007/11/10.16:29:21
FL E:/资料/计算机设计与实践/MyCPU16/CPU_16.vhdl 2007/11/12.10:18:50
FL e:/资料/计算机设计与实践/mycpu16/code.vhdl 2007/11/10.16:28:55
FL $XILINX/bin/MyCPU16/memory.vhdl 2007/11/10.16:29:22
FL E:/资料/计算机设计与实践/MyCPU16/memory.vhdl 2007/11/10.16:29:21
FL $XILINX/bin/MyCPU16/code.vhdl 2007/11/10.16:28:56
FL F:/MyCPU16/visit_memory.vhdl 2007/11/22.17:49:52
EN work/VISIT_MEMORY    FL F:/MyCPU16/visit_memory.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED PH unisim/VCOMPONENTS
AR work/VISIT_MEMORY/BEHAVIORAL FL F:/MyCPU16/visit_memory.vhdl \
      EN work/VISIT_MEMORY CP BUFGP
FL I:/MyCPU16/CPU_16.vhdl 2007/11/22.17:31:02
EN work/CPU_16          FL I:/MyCPU16/CPU_16.vhdl PB ieee/STD_LOGIC_1164 \
      PH unisim/VCOMPONENTS
AR work/CPU_16/BEHAVIORAL FL I:/MyCPU16/CPU_16.vhdl EN work/CPU_16 CP BUFGP \
      CP ALU            CP CLOCK          CP CODE           CP MEMORY \
      CP VISIT_MEMORY   CP WRITE_BACK
FL I:/MyCPU16/code.vhdl 2007/11/22.17:49:48
FL I:/MyCPU16/ALU.vhdl 2007/11/22.17:49:42
FL E:/资料/计算机设计与实践/MyCPU16/clock.vhdl 2007/11/10.16:28:45
FL F:/MyCPU16/write_back.vhdl 2007/11/22.17:49:54
EN work/WRITE_BACK      FL F:/MyCPU16/write_back.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED PH unisim/VCOMPONENTS
AR work/WRITE_BACK/BEHAVIORAL FL F:/MyCPU16/write_back.vhdl EN work/WRITE_BACK \
      CP BUFGP
FL E:/资料/计算机设计与实践/MyCPU16/ALU.vhdl 2007/11/10.16:14:42
FL e:/资料/计算机设计与实践/mycpu16/ALU.vhdl 2007/11/10.16:14:42
FL $XILINX/bin/MyCPU16/write_back.vhdl 2007/11/10.16:41:04
FL F:/MyCPU16/clock.vhdl 2007/11/22.17:49:44
EN work/CLOCK           FL F:/MyCPU16/clock.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PH unisim/VCOMPONENTS
AR work/CLOCK/BEHAVIORAL FL F:/MyCPU16/clock.vhdl EN work/CLOCK CP BUFGP
FL E:/资料/计算机设计与实践/MyCPU16/visit_memory.vhdl 2007/11/10.16:54:50
FL e:/资料/计算机设计与实践/mycpu16/visit_memory.vhdl 2007/11/10.16:54:50
FL I:/MyCPU16/memory.vhdl 2007/11/10.16:29:22
EN work/MEMORY          FL I:/MyCPU16/memory.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED PH unisim/VCOMPONENTS
AR work/MEMORY/BEHAVIORAL FL I:/MyCPU16/memory.vhdl EN work/MEMORY
FL I:/MyCPU16/write_back.vhdl 2007/11/22.17:49:54
FL F:/MyCPU16/CPU_16.vhdl 2007/11/12.10:18:52
FL e:/资料/计算机设计与实践/mycpu16/CPU_16.vhdl 2007/11/10.16:30:41
FL $XILINX/bin/MyCPU16/CPU_16.vhdl 2007/11/12.10:18:52
FL E:/资料/计算机设计与实践/MyCPU16/code.vhdl 2007/11/10.16:28:55
FL e:/资料/计算机设计与实践/mycpu16/write_back.vhdl 2007/11/10.16:41:03
FL $XILINX/bin/MyCPU16/ALU.vhdl 2007/11/10.16:14:44
FL I:/MyCPU16/clock.vhdl 2007/11/22.17:49:44
FL I:/MyCPU16/visit_memory.vhdl 2007/11/22.17:49:52
FL $XILINX/bin/MyCPU16/clock.vhdl 2007/11/10.16:28:46