hdllib.ref

CPU 设计

EN clock NULL F:/MyCPU16/clock.vhdl sub00/vhpl04
AR cpu16 behavioral I:/MyCPU16/CPU_16.vhdl sub00/vhpl15
EN visit_memory NULL F:/MyCPU16/visit_memory.vhdl sub00/vhpl10
AR alu behavioral F:/MyCPU16/ALU.vhdl sub00/vhpl03
EN cpu_16 NULL I:/MyCPU16/CPU_16.vhdl sub00/vhpl00
AR visit_memory behavioral F:/MyCPU16/visit_memory.vhdl sub00/vhpl11
AR code behavioral F:/MyCPU16/code.vhdl sub00/vhpl07
AR clock behavioral F:/MyCPU16/clock.vhdl sub00/vhpl05
EN memory NULL I:/MyCPU16/memory.vhdl sub00/vhpl08
EN code NULL F:/MyCPU16/code.vhdl sub00/vhpl06
AR memory behavioral I:/MyCPU16/memory.vhdl sub00/vhpl09
EN cpu16 NULL I:/MyCPU16/CPU_16.vhdl sub00/vhpl14
EN write_back NULL F:/MyCPU16/write_back.vhdl sub00/vhpl12
AR write_back behavioral F:/MyCPU16/write_back.vhdl sub00/vhpl13
AR cpu_16 behavioral I:/MyCPU16/CPU_16.vhdl sub00/vhpl01
EN alu NULL F:/MyCPU16/ALU.vhdl sub00/vhpl02