wch_fht.vqm

AlteraFPGACPLD设计高级篇电子书籍

//
// Written by Synplify
// Synplify 7.3.5, Build 250R.
// Wed Dec 22 23:53:47 2004
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\prj_d\example-s1-1\fht_example\after_optimized\wch_fht.v "

module wch_fht (
  Clk,
  Reset,
  PreFhtStar,
  In0,
  In1,
  In2,
  In3,
  In4,
  In5,
  In6,
  In7,
  In8,
  In9,
  In10,
  In11,
  In12,
  In13,
  In14,
  In15,
  Out0,
  Out1,
  Out2,
  Out3,
  Out4,
  Out5,
  Out6,
  Out7,
  Out8,
  Out9,
  Out10,
  Out11,
  Out12,
  Out13,
  Out14,
  Out15
);
input Clk ;
input Reset ;
input PreFhtStar ;
input [11:0] In0 ;
input [11:0] In1 ;
input [11:0] In2 ;
input [11:0] In3 ;
input [11:0] In4 ;
input [11:0] In5 ;
input [11:0] In6 ;
input [11:0] In7 ;
input [11:0] In8 ;
input [11:0] In9 ;
input [11:0] In10 ;
input [11:0] In11 ;
input [11:0] In12 ;
input [11:0] In13 ;
input [11:0] In14 ;
input [11:0] In15 ;
output [15:0] Out0 ;
output [15:0] Out1 ;
output [15:0] Out2 ;
output [15:0] Out3 ;
output [15:0] Out4 ;
output [15:0] Out5 ;
output [15:0] Out6 ;
output [15:0] Out7 ;
output [15:0] Out8 ;
output [15:0] Out9 ;
output [15:0] Out10 ;
output [15:0] Out11 ;
output [15:0] Out12 ;
output [15:0] Out13 ;
output [15:0] Out14 ;
output [15:0] Out15 ;
wire Clk ;
wire Reset ;
wire PreFhtStar ;
wire [2:0] Cnt3_i_0;
wire [15:0] Temp7_x;
wire [15:0] Temp15_x;
wire [15:0] Temp6_x;
wire [15:0] Temp14_x;
wire [15:0] Temp5_x;
wire [15:0] Temp13_x;
wire [15:0] Temp4_x;
wire [15:0] Temp12_x;
wire [15:0] Temp3_x;
wire [15:0] Temp11_x;
wire [15:0] Temp2_x;
wire [15:0] Temp10_x;
wire [15:0] Temp1_x;
wire [15:0] Temp9_x;
wire [15:0] Temp0_x;
wire [15:0] Temp8_x;
wire VCC ;
wire GND ;
wire Out913 ;
wire un3_Out15_carry_14 ;
wire un3_Out15_carry_13 ;
wire un3_Out15_carry_12 ;
wire un3_Out15_carry_11 ;
wire un3_Out15_carry_10 ;
wire un3_Out15_carry_9 ;
wire un3_Out15_carry_8 ;
wire un3_Out15_carry_7 ;
wire un3_Out15_carry_6 ;
wire un3_Out15_carry_5 ;
wire un3_Out15_carry_4 ;
wire un3_Out15_carry_3 ;
wire un3_Out15_carry_2 ;
wire un3_Out15_carry_1 ;
wire un3_Out15_carry_0 ;
wire un3_Out13_carry_14 ;
wire un3_Out13_carry_13 ;
wire un3_Out13_carry_12 ;
wire un3_Out13_carry_11 ;
wire un3_Out13_carry_10 ;
wire un3_Out13_carry_9 ;
wire un3_Out13_carry_8 ;
wire un3_Out13_carry_7 ;
wire un3_Out13_carry_6 ;
wire un3_Out13_carry_5 ;
wire un3_Out13_carry_4 ;
wire un3_Out13_carry_3 ;
wire un3_Out13_carry_2 ;
wire un3_Out13_carry_1 ;
wire un3_Out13_carry_0 ;
wire un3_Out11_carry_14 ;
wire un3_Out11_carry_13 ;
wire un3_Out11_carry_12 ;
wire un3_Out11_carry_11 ;
wire un3_Out11_carry_10 ;
wire un3_Out11_carry_9 ;
wire un3_Out11_carry_8 ;
wire un3_Out11_carry_7 ;
wire un3_Out11_carry_6 ;
wire un3_Out11_carry_5 ;
wire un3_Out11_carry_4 ;
wire un3_Out11_carry_3 ;
wire un3_Out11_carry_2 ;
wire un3_Out11_carry_1 ;
wire un3_Out11_carry_0 ;
wire un3_Out9_carry_14 ;
wire un3_Out9_carry_13 ;
wire un3_Out9_carry_12 ;
wire un3_Out9_carry_11 ;
wire un3_Out9_carry_10 ;
wire un3_Out9_carry_9 ;
wire un3_Out9_carry_8 ;
wire un3_Out9_carry_7 ;
wire un3_Out9_carry_6 ;
wire un3_Out9_carry_5 ;
wire un3_Out9_carry_4 ;
wire un3_Out9_carry_3 ;
wire un3_Out9_carry_2 ;
wire un3_Out9_carry_1 ;
wire un3_Out9_carry_0 ;
wire un3_Out7_carry_14 ;
wire un3_Out7_carry_13 ;
wire un3_Out7_carry_12 ;
wire un3_Out7_carry_11 ;
wire un3_Out7_carry_10 ;
wire un3_Out7_carry_9 ;
wire un3_Out7_carry_8 ;
wire un3_Out7_carry_7 ;
wire un3_Out7_carry_6 ;
wire un3_Out7_carry_5 ;
wire un3_Out7_carry_4 ;
wire un3_Out7_carry_3 ;
wire un3_Out7_carry_2 ;
wire un3_Out7_carry_1 ;
wire un3_Out7_carry_0 ;
wire un3_Out5_carry_14 ;
wire un3_Out5_carry_13 ;
wire un3_Out5_carry_12 ;
wire un3_Out5_carry_11 ;
wire un3_Out5_carry_10 ;
wire un3_Out5_carry_9 ;
wire un3_Out5_carry_8 ;
wire un3_Out5_carry_7 ;
wire un3_Out5_carry_6 ;
wire un3_Out5_carry_5 ;
wire un3_Out5_carry_4 ;
wire un3_Out5_carry_3 ;
wire un3_Out5_carry_2 ;
wire un3_Out5_carry_1 ;
wire un3_Out5_carry_0 ;
wire un3_Out3_carry_14 ;
wire un3_Out3_carry_13 ;
wire un3_Out3_carry_12 ;
wire un3_Out3_carry_11 ;
wire un3_Out3_carry_10 ;
wire un3_Out3_carry_9 ;
wire un3_Out3_carry_8 ;
wire un3_Out3_carry_7 ;
wire un3_Out3_carry_6 ;
wire un3_Out3_carry_5 ;
wire un3_Out3_carry_4 ;
wire un3_Out3_carry_3 ;
wire un3_Out3_carry_2 ;
wire un3_Out3_carry_1 ;
wire un3_Out3_carry_0 ;
wire un3_Out1_carry_14 ;
wire un3_Out1_carry_13 ;
wire un3_Out1_carry_12 ;
wire un3_Out1_carry_11 ;
wire un3_Out1_carry_10 ;
wire un3_Out1_carry_9 ;
wire un3_Out1_carry_8 ;
wire un3_Out1_carry_7 ;
wire un3_Out1_carry_6 ;
wire un3_Out1_carry_5 ;
wire un3_Out1_carry_4 ;
wire un3_Out1_carry_3 ;
wire un3_Out1_carry_2 ;
wire un3_Out1_carry_1 ;
wire un3_Out1_carry_0 ;
wire un3_Out14_carry_14 ;
wire un3_Out14_carry_13 ;
wire un3_Out14_carry_12 ;
wire un3_Out14_carry_11 ;
wire un3_Out14_carry_10 ;
wire un3_Out14_carry_9 ;
wire un3_Out14_carry_8 ;
wire un3_Out14_carry_7 ;
wire un3_Out14_carry_6 ;
wire un3_Out14_carry_5 ;
wire un3_Out14_carry_4 ;
wire un3_Out14_carry_3 ;
wire un3_Out14_carry_2 ;
wire un3_Out14_carry_1 ;
wire un3_Out14_carry_0 ;
wire un3_Out12_carry_14 ;
wire un3_Out12_carry_13 ;
wire un3_Out12_carry_12 ;
wire un3_Out12_carry_11 ;
wire un3_Out12_carry_10 ;
wire un3_Out12_carry_9 ;
wire un3_Out12_carry_8 ;
wire un3_Out12_carry_7 ;
wire un3_Out12_carry_6 ;
wire un3_Out12_carry_5 ;
wire un3_Out12_carry_4 ;
wire un3_Out12_carry_3 ;
wire un3_Out12_carry_2 ;
wire un3_Out12_carry_1 ;
wire un3_Out12_carry_0 ;
wire un3_Out10_carry_14 ;
wire un3_Out10_carry_13 ;
wire un3_Out10_carry_12 ;
wire un3_Out10_carry_11 ;
wire un3_Out10_carry_10 ;
wire un3_Out10_carry_9 ;
wire un3_Out10_carry_8 ;
wire un3_Out10_carry_7 ;
wire un3_Out10_carry_6 ;
wire un3_Out10_carry_5 ;
wire un3_Out10_carry_4 ;
wire un3_Out10_carry_3 ;
wire un3_Out10_carry_2 ;
wire un3_Out10_carry_1 ;
wire un3_Out10_carry_0 ;
wire un3_Out8_carry_14 ;
wire un3_Out8_carry_13 ;
wire un3_Out8_carry_12 ;
wire un3_Out8_carry_11 ;
wire un3_Out8_carry_10 ;
wire un3_Out8_carry_9 ;
wire un3_Out8_carry_8 ;
wire un3_Out8_carry_7 ;
wire un3_Out8_carry_6 ;
wire un3_Out8_carry_5 ;
wire un3_Out8_carry_4 ;
wire un3_Out8_carry_3 ;
wire un3_Out8_carry_2 ;
wire un3_Out8_carry_1 ;
wire un3_Out8_carry_0 ;
wire un3_Out6_carry_14 ;
wire un3_Out6_carry_13 ;
wire un3_Out6_carry_12 ;
wire un3_Out6_carry_11 ;
wire un3_Out6_carry_10 ;
wire un3_Out6_carry_9 ;
wire un3_Out6_carry_8 ;
wire un3_Out6_carry_7 ;
wire un3_Out6_carry_6 ;
wire un3_Out6_carry_5 ;
wire un3_Out6_carry_4 ;
wire un3_Out6_carry_3 ;
wire un3_Out6_carry_2 ;
wire un3_Out6_carry_1 ;
wire un3_Out6_carry_0 ;
wire un3_Out4_carry_14 ;
wire un3_Out4_carry_13 ;
wire un3_Out4_carry_12 ;
wire un3_Out4_carry_11 ;
wire un3_Out4_carry_10 ;
wire un3_Out4_carry_9 ;
wire un3_Out4_carry_8 ;
wire un3_Out4_carry_7 ;
wire un3_Out4_carry_6 ;
wire un3_Out4_carry_5 ;
wire un3_Out4_carry_4 ;
wire un3_Out4_carry_3 ;
wire un3_Out4_carry_2 ;
wire un3_Out4_carry_1 ;
wire un3_Out4_carry_0 ;
wire un3_Out2_carry_14 ;
wire un3_Out2_carry_13 ;
wire un3_Out2_carry_12 ;
wire un3_Out2_carry_11 ;
wire un3_Out2_carry_10 ;
wire un3_Out2_carry_9 ;
wire un3_Out2_carry_8 ;
wire un3_Out2_carry_7 ;
wire un3_Out2_carry_6 ;
wire un3_Out2_carry_5 ;
wire un3_Out2_carry_4 ;
wire un3_Out2_carry_3 ;
wire un3_Out2_carry_2 ;
wire un3_Out2_carry_1 ;
wire un3_Out2_carry_0 ;
wire un3_Out0_carry_14 ;
wire un3_Out0_carry_13 ;
wire un3_Out0_carry_12 ;
wire un3_Out0_carry_11 ;
wire un3_Out0_carry_10 ;
wire un3_Out0_carry_9 ;
wire un3_Out0_carry_8 ;
wire un3_Out0_carry_7 ;
wire un3_Out0_carry_6 ;
wire un3_Out0_carry_5 ;
wire un3_Out0_carry_4 ;
wire un3_Out0_carry_3 ;
wire un3_Out0_carry_2 ;
wire un3_Out0_carry_1 ;
wire un3_Out0_carry_0 ;
wire FhtEn ;
wire un1_PreFhtStar_1_i ;
wire Reset_i ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @1:23
  cyclone_lcell Cnt3_i_0_2_ (
	.regout(Cnt3_i_0[2]),
	.clk(Clk),
	.dataa(PreFhtStar),
	.datab(Cnt3_i_0[0]),
	.datac(Cnt3_i_0[1]),
	.datad(Cnt3_i_0[2]),
	.aclr(Reset_i)
);
defparam Cnt3_i_0_2_.operation_mode="normal";
defparam Cnt3_i_0_2_.output_mode="reg_only";
defparam Cnt3_i_0_2_.lut_mask="1540";
defparam Cnt3_i_0_2_.synch_mode="off";
defparam Cnt3_i_0_2_.sum_lutc_input="datac";
// @1:23
  cyclone_lcell Cnt3_i_0_1_ (
	.regout(Cnt3_i_0[1]),
	.clk(Clk),
	.dataa(PreFhtStar),
	.datab(Cnt3_i_0[0]),
	.datac(Cnt3_i_0[1]),
	.aclr(Reset_i)
);
defparam Cnt3_i_0_1_.operation_mode="normal";
defparam Cnt3_i_0_1_.output_mode="reg_only";
defparam Cnt3_i_0_1_.lut_mask="bebe";
defparam Cnt3_i_0_1_.synch_mode="off";
defparam Cnt3_i_0_1_.sum_lutc_input="datac";
// @1:23
  cyclone_lcell Cnt3_i_0_0_ (
	.regout(Cnt3_i_0[0]),
	.clk(Clk),
	.dataa(PreFhtStar),
	.datab(Cnt3_i_0[0]),
	.aclr(Reset_i)
);
defparam Cnt3_i_0_0_.operation_mode="normal";
defparam Cnt3_i_0_0_.output_mode="reg_only";
defparam Cnt3_i_0_0_.lut_mask="bbbb";
defparam Cnt3_i_0_0_.synch_mode="off";
defparam Cnt3_i_0_0_.sum_lutc_input="datac";
// @1:68
  cyclone_lcell Out15_15_ (
	.regout(Out15[15]),
	.clk(Clk),
	.dataa(Temp7_x[15]),
	.datab(Temp15_x[15]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_14)
);
defparam Out15_15_.cin_used="true";
defparam Out15_15_.operation_mode="normal";
defparam Out15_15_.output_mode="reg_only";
defparam Out15_15_.lut_mask="6969";
defparam Out15_15_.synch_mode="off";
defparam Out15_15_.sum_lutc_input="cin";
// @1:68
  cyclone_lcell Out15_14_ (
	.regout(Out15[14]),
	.cout(un3_Out15_carry_14),
	.clk(Clk),
	.dataa(Temp7_x[14]),
	.datab(Temp15_x[14]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_13)
);
defparam Out15_14_.cin_used="true";
defparam Out15_14_.operation_mode="arithmetic";
defparam Out15_14_.output_mode="reg_only";
defparam Out15_14_.lut_mask="69b2";
defparam Out15_14_.synch_mode="off";
defparam Out15_14_.sum_lutc_input="cin";
// @1:68
  cyclone_lcell Out15_13_ (
	.regout(Out15[13]),
	.cout(un3_Out15_carry_13),
	.clk(Clk),
	.dataa(Temp7_x[13]),
	.datab(Temp15_x[13]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_12)
);
defparam Out15_13_.cin_used="true";
defparam Out15_13_.operation_mode="arithmetic";
defparam Out15_13_.output_mode="reg_only";
defparam Out15_13_.lut_mask="69b2";
defparam Out15_13_.synch_mode="off";
defparam Out15_13_.sum_lutc_input="cin";
// @1:68
  cyclone_lcell Out15_12_ (
	.regout(Out15[12]),
	.cout(un3_Out15_carry_12),
	.clk(Clk),
	.dataa(Temp7_x[12]),
	.datab(Temp15_x[12]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_11)
);
defparam Out15_12_.cin_used="true";
defparam Out15_12_.operation_mode="arithmetic";
defparam Out15_12_.output_mode="reg_only";
defparam Out15_12_.lut_mask="69b2";
defparam Out15_12_.synch_mode="off";
defparam Out15_12_.sum_lutc_input="cin";
// @1:68
  cyclone_lcell Out15_11_ (
	.regout(Out15[11]),
	.cout(un3_Out15_carry_11),
	.clk(Clk),
	.dataa(Temp7_x[11]),
	.datab(Temp15_x[11]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_10)
);
defparam Out15_11_.cin_used="true";
defparam Out15_11_.operation_mode="arithmetic";
defparam Out15_11_.output_mode="reg_only";
defparam Out15_11_.lut_mask="69b2";
defparam Out15_11_.synch_mode="off";
defparam Out15_11_.sum_lutc_input="cin";
// @1:68
  cyclone_lcell Out15_10_ (
	.regout(Out15[10]),
	.cout(un3_Out15_carry_10),
	.clk(Clk),
	.dataa(Temp7_x[10]),
	.datab(Temp15_x[10]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_9)
);
defparam Out15_10_.cin_used="true";
defparam Out15_10_.operation_mode="arithmetic";
defparam Out15_10_.output_mode="reg_only";
defparam Out15_10_.lut_mask="69b2";
defparam Out15_10_.synch_mode="off";
defparam Out15_10_.sum_lutc_input="cin";
// @1:68
  cyclone_lcell Out15_9_ (
	.regout(Out15[9]),
	.cout(un3_Out15_carry_9),
	.clk(Clk),
	.dataa(Temp7_x[9]),
	.datab(Temp15_x[9]),
	.aclr(Reset_i),
	.ena(Out913),
	.cin(un3_Out15_carry_8)
);
defparam Out15_9_.cin_used="true";