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📁 Memory Management—Algorithms and implementation in C/C++ Introduction Chapter 1 - Memory Manag
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<h2 class="first-section-title"><a name="65"></a><a name="ch01lev1sec3"></a>Address Lines and Buses</h2><a name="66"></a><a name="IDX-9"></a>
<p class="para">Each byte in DRAM is assigned a unique numeric identifier called an <i class="emphasis">address</i>, just like houses on a street. An address is an integer value. The first byte in memory is assigned an address of zero. The region of memory near address zero is known as the <i class="emphasis">bottom of memory</i>, or <i class="emphasis">low memory</i>. The region of memory near the final byte is known as <i class="emphasis">high memory</i>. The number of physical (i.e., DRAM) bytes that a processor is capable of addressing is known as the processor's <i class="emphasis">physical address space</i>. (See <a class="internaljump" href="#ch01fig03">Figure 1.3</a>.)</p>
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<span class="figure-title"><span class="figure-titlelabel">Figure 1.3</span></span>
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<p class="para">The physical address space of a processor specifies the <i class="emphasis">potential</i> number of bytes that can be addressed, <i class="emphasis">not</i> the actual number of physical bytes present. People normally don't want to spend the money necessary to populate the entire physical address space with DRAM chips. Buying 4GB of DRAM is still usually reserved for high-end enterprise servers.</p>
<p class="para">The physical address space of a processor is determined by the number of address lines that it has. Address lines are a set of wires connecting the processor to its DRAM chips. Each address line specifies a single bit in the address of a given byte. For example, the Intel Pentium has 32 address lines. This means that each byte is assigned a 32-bit address so that its address space consists of 2<sup>32</sup> addressable bytes (4GB). The 8088 had 20 address lines, so it was capable of addressing 2<sup>20</sup>, or 1,048,576, bytes.</p>
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<p class="first-para">If virtual memory is enabled on the Pentium 4, there is a way to enable four additional address lines using what is known as Physical Address Extension (PAE). This allows the Pentium processor's physical address space to be defined by 36 address lines, which translates into an address space of 2<sup>36</sup> bytes (64GB).</p>
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<p class="para">To access and update physical memory, the processor uses a control bus and a data bus. A <i class="emphasis">bus</i> is a collection of related wires that connect the processor to a hardware subsystem. The control bus is used to indicate if the processor wants to read from memory or write to memory. The data bus is used to ferry data back and forth between the processor and memory. (See <a class="internaljump" href="#ch01fig04">Figure 1.4</a>.)</p>
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<span class="figure-title"><span class="figure-titlelabel">Figure 1.4</span></span>
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<p class="para">When the processor reads from memory, the following steps are performed:</p>
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<p class="first-para">The processor places the address of the byte to be read on the address lines.</p>
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<p class="first-para">The processor sends the read signal on the control bus.</p>
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<p class="first-para">The DRAM chip(s) return the byte specified on the data bus.</p>
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<p class="para">When the processor writes to memory, the following steps are performed:</p>
<ol class="orderedlist">
<li class="first-listitem">
<p class="first-para">The processor places the address of the byte to be written on the address lines.</p>
</li>
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<p class="first-para">The processor sends the write signal on the control bus.</p>
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<p class="first-para">The processor sends the byte to be written to memory on the data bus.</p>
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<p class="last-para">This description is somewhat of an oversimplification. For example, the Pentium processor reads and writes data 4 bytes at a time. This is one reason why the Pentium is called a 32-bit chip. The processor will refer to its 32-bit payload using the address of the first byte (i.e., the byte with the lowest address). Nevertheless, I think the general operation is clear.</p>
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