📄 the mathworks deutschland - filter design toolbox - implementing the filter chain of a digital down-converter in hdl demo.htm
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<P>However, here we will use the command line functionality to
generate the HDL code.</P>
<P>Now that we have our fixed-point, three-stage, multirate filter
meeting the specs we are ready to generate HDL code.</P>
<P>Cascade of CIC and two FIR filters and generate VHDL. Note that
we're not using the normalized CIC for code generation. The
normalized CIC was used for visualization purposes only. </P><PRE class=code>hcas = cascade(hcic,hcfir,hpfir);
workingdir = tempname;
generatehdl(hcas,<SPAN class=string>'Name'</SPAN>,<SPAN class=string>'filter'</SPAN>,<SPAN class=string>'TargetLanguage'</SPAN>,<SPAN class=string>'VHDL'</SPAN>,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'TargetDirectory'</SPAN>,fullfile(workingdir,<SPAN class=string>'hdlsrc'</SPAN>));
</PRE><PRE class=ans>### Starting VHDL code generation process for filter: filter
### Cascade stage # 1
### Starting VHDL code generation process for filter: filter_stage1
### Generating: C:\TEMP\R2008ad_169\3796\tp7b6c71a1_c23b_42c0_a950_9be0bd1dc
ddb\hdlsrc\filter_stage1.vhd
### Starting generation of filter_stage1 VHDL entity
### Starting generation of filter_stage1 VHDL architecture
### Section # 1 : Integrator
### Section # 2 : Integrator
### Section # 3 : Integrator
### Section # 4 : Integrator
### Section # 5 : Integrator
### Section # 6 : Comb
### Section # 7 : Comb
### Section # 8 : Comb
### Section # 9 : Comb
### Section # 10 : Comb
### HDL latency is 1 samples
### Successful completion of VHDL code generation process for filter: filter
_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: filter_stage2
### Generating: C:\TEMP\R2008ad_169\3796\tp7b6c71a1_c23b_42c0_a950_9be0bd1dc
ddb\hdlsrc\filter_stage2.vhd
### Starting generation of filter_stage2 VHDL entity
### Starting generation of filter_stage2 VHDL architecture
### HDL latency is 0 samples
### Successful completion of VHDL code generation process for filter: filter
_stage2
### Cascade stage # 3
### Starting VHDL code generation process for filter: filter_stage3
### Generating: C:\TEMP\R2008ad_169\3796\tp7b6c71a1_c23b_42c0_a950_9be0bd1dc
ddb\hdlsrc\filter_stage3.vhd
### Starting generation of filter_stage3 VHDL entity
### Starting generation of filter_stage3 VHDL architecture
### HDL latency is 1 samples
### Successful completion of VHDL code generation process for filter: filter
_stage3
### Generating: C:\TEMP\R2008ad_169\3796\tp7b6c71a1_c23b_42c0_a950_9be0bd1dc
ddb\hdlsrc\filter.vhd
### Starting generation of filter VHDL entity
### Starting generation of filter VHDL architecture
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: filter
</PRE>
<H3>HDL Co-simulation with ModelSim® in Simulink®<A
name=25></A></H3>
<P>To verify that the generated HDL code is producing the same
results as our Simulink® model, we'll use EDA Simulator Link™ MS to
co-simulate our HDL code in Simulink. We have a pre-built Simulink
model that includes two signal paths. One signal path produces
Simulink's behavioral model results of the three-stage, multirate
filter. The other path produces the results of simulating, with
ModelSim, the VHDL code we generated. </P><PRE class=code>open_system(<SPAN class=string>'ddcdemocosim.mdl'</SPAN>);
</PRE><A
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width=350 vspace=5></A>
<P>For the behavioral model simulation we will generate a Simulink
block of the three-stage, multirate filter we designed and place
that block in the Simulink model where we'll co-simulate with
ModelSim. </P><PRE class=code><SPAN class=comment>% Generate Simulink block of cascaded filters. Change the compensating</SPAN>
<SPAN class=comment>% filter's default rounding mode because it's not supported in Simulink.</SPAN>
set(hcfir,<SPAN class=string>'FilterInternals'</SPAN>,<SPAN class=string>'SpecifyPrecision'</SPAN>,<SPAN class=string>'RoundMode'</SPAN>,<SPAN class=string>'round'</SPAN>);
block(hcas,<SPAN class=string>'OverwriteBlock'</SPAN>,<SPAN class=string>'on'</SPAN>);
open_system(<SPAN class=string>'ddcdemocosim.mdl'</SPAN>);
<SPAN class=comment>% Start ModelSim. Uncomment the following lines of code to compile and load</SPAN>
<SPAN class=comment>% the HDL code in ModelSim. Note that ModelSim must be installed and on</SPAN>
<SPAN class=comment>% the system path.</SPAN>
<SPAN class=comment>%</SPAN>
<SPAN class=comment>% cachepwd = pwd;</SPAN>
<SPAN class=comment>% cd(workingdir) % Go to directory where code was generated.</SPAN>
<SPAN class=comment>% vsim('tclstart',ddcdemolinkcmds,'socketsimulink',4449);</SPAN>
</PRE><PRE class=ans>Warning: The 'round' round mode is not supported by the Signal Processing
Blockset. Converting to 'Nearest'.
Warning: The 'round' round mode is not supported by the Signal Processing
Blockset. Converting to 'Nearest'.
Warning: The 'round' round mode is not supported by the Signal Processing
Blockset. Converting to 'Nearest'.
Warning: The 'round' round mode is not supported by the Signal Processing
Blockset. Converting to 'Nearest'.
</PRE>
<P>Note that the warnings generated are due to the fact that the
input quantization settings are set explicitly in the filter
objects, but are inherited in Simulink's filter block. </P><PRE class=code><SPAN class=comment>% Run Simulink simulation and open the Scope to view results. Uncomment</SPAN>
<SPAN class=comment>% the following lines to run the simulation. Note that you must first</SPAN>
<SPAN class=comment>% uncomment the code above that starts ModelSim.</SPAN>
<SPAN class=comment>%</SPAN>
<SPAN class=comment>% pause(5);</SPAN>
<SPAN class=comment>% sim('ddcdemocosim');</SPAN>
<SPAN class=comment>% open_system('ddcdemocosim/Verification_Results/Time Scope');</SPAN>
<SPAN class=comment>% cd(cachepwd)</SPAN>
</PRE>
<P>The warnings generated when running the code are due to the fact
that the coefficients are stored as doubles when specified in the
filter block, and therefore will be quantized to the word length and
fractional length specified in the filter object. </P>
<P>The scope below displays the results of running the
simulation.</P>
<P><IMG hspace=5
src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcdemoscope.png"
vspace=5> </P>
<H3>Verifying Results<A name=30></A></H3>
<P>The trace on the top is the excitation chirp signal. The next
signal labeled "ref" is the reference signal produced by the
Simulink behavioral model of the three-stage multirate filter. The
bottom trace labeled "cosim" on the scope is of the ModelSim
simulation results of the generated HDL code of the three-stage
multirate filter. The last trace shows the error between Simulink's
behavioral model results and ModelSim's simulation of the HDL code.
</P>
<H3>Summary<A name=31></A></H3>
<P>We used several MathWorks products to design and analyze a
three-stage, multirate, fixed-point filter chain of a DDC for a GSM
application. Then we generated HDL code to implement the filter and
verified the generated code by comparing Simulink's behavioral model
with HDL code simulated in ModelSim via EDA Simulator Link™ MS.
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