the mathworks deutschland - filter design toolbox - implementing the filter chain of a digital down-converter in hdl demo.htm

用于数字下变频器的 FPGA 实现

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            <H1>Signal Processing and Communications</H1>
            <H2>Implementing the Filter Chain of a Digital Down-Converter in 
            HDL</H2>
            <P>This demo uses the Filter Design Toolbox™ and Fixed-Point 
            Toolbox™ to design a three-stage, multirate, fixed-point filter that 
            implements the filter chain of a Digital Down-Converter (DDC) 
            designed to meet the Global System for Mobile (GSM) specification. 
            </P>
            <P>Using the Filter Design HDL Coder™ we will generate synthesizable 
            HDL code for the same three-stage, multirate, fixed-point filter. 
            Finally, using Simulink® and EDA Simulator Link™ MS, we will 
            co-simulate the fixed-point filters to verify that the generated HDL 
            code produces the same results as the equivalent Simulink behavioral 
            model. </P>
            <H3>Contents</H3>
            <DIV>
            <UL>
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#1">Digital 
              Down-Converter</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#3">GSM 
              Specifications</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#5">Cascaded 
              Integrator-Comb (CIC) Filter</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#11">Compensation 
              FIR Decimator</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#15">Third 
              Stage FIR Decimator</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#19">Multistage 
              Multirate DDC Filter Chain</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#23">Generate 
              VHDL Code</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#25">HDL 
              Co-simulation with ModelSim® in Simulink®</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#30">Verifying 
              Results</A> 
              <LI><A 
              href="http://www.mathworks.de/applications/dsp_comm/demos.html?file=/products/demos/shipping/filterdesign/ddcfilterchaindemo.html#31">Summary</A> 
              </LI></UL></DIV>
            <H3>Digital Down-Converter<A name=1></A></H3>
            <P>Digital Down-Converters (DDC) are a key component of digital 
            radios. The DDC performs the frequency translation necessary to 
            convert the high input sample rates found in a digital radio, down 
            to lower sample rates for further and easier processing. In this 
            example, the DDC operates at approximately 70 MHz and must reduce 
            the rate down to 270 KHz. </P>
            <P>To further constrain our problem we will model one of the DDCs in 
            Graychip?s GC4016 Multi-Standard Quad DDC Chip. The GC4016, among 
            other features, provides the following filters: a five-stage CIC 
            filter with programmable decimation factor (8-4096); a 21-tap FIR 
            filter which decimates by 2 and has programmable 16-bit 
            coefficients; and a 63-tap FIR filter which also decimates by 2 and 
            has programmable 16-bit coefficients. </P>
            <P>The DDC consists of a Numeric Controlled Oscillator (NCO) and a 
            mixer to quadrature down convert the input signal to baseband. The 
            baseband signal is then low pass filtered by a Cascaded 
            Integrator-Comb (CIC) filter followed by two FIR decimating filters 
            to achieve a low sample-rate of about 270 KHz ready for further 
            processing. The final stage often includes a resampler which 
            interpolates or decimates the signal to achieve the desired sample 
            rate depending on the application. Further filtering can also be 
            achieved with the resampler. A block diagram of a typical DDC is 
            shown below. </P>
            <P><A 
            onmouseover="window.status='Click to enlarge image.'; return true;" 
            onclick="openWindow('/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcdemomodel.png',632,558, 'scrollbars=no,resizable=yes,status=no'); return false;" 
            onmouseout="window.status='';" 
            href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcdemomodel.png"><IMG 
            height=309 hspace=5 
            src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcdemomodel_thumbnail.png" 
            width=350 vspace=5></A> </P>
            <P>This demo focuses on the three-stage, multirate, decimation 
            filter, which consists of the CIC and the two decimating FIR 
            filters.</P>
            <H3>GSM Specifications<A name=3></A></H3>
            <P>The GSM bandwidth of interest is 160 KHz. Therefore, the DDC's 
            three-stage, multirate filter response must be flat over this 
            bandwidth to within the passband ripple, which must be less than 0.1 
            dB peak to peak. Looking at the GSM out of band rejection mask shown 
            below, we see that the filter must also achieve 18 dB of attenuation 
            at 100 KHz. </P>
            <P><IMG hspace=5 
            src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcdemogsmmask.png" 
            vspace=5> </P>
            <P>In addition, GSM requires a symbol rate of 270.833 Ksps. Since 
            the Graychip's input sample rate is the same as its clock rate of 
            69.333 MHz, we must downsample the input down to 270.833 KHz. This 
            requires that the three-stage, multirate filter decimate by 256. 
</P>
            <H3>Cascaded Integrator-Comb (CIC) Filter<A name=5></A></H3>
            <P>CIC filters are multirate filters that are very useful because 
            they can achieve high decimation (or interpolation) rates and are 
            implemented without multipliers. CICs are simply boxcar filters 
            implemented recursively cascaded with an upsampler or downsampler. 
            These characteristic make CICs very useful for digital systems 
            operating at high rates, especially when these systems are to be 
            implemented in ASICs or FPGAs. </P>
            <P>Although CICs have desirable characteristics they also have some 
            drawbacks, most notably the fact that they incur attenuation in the 
            passband region due to their sinc-like response. For that reason 
            CICs often have to be followed by a compensating filter. The 
            compensating filter must have an inverse-sinc response in the 
            passband region to lift the droop caused by the CIC. </P>
            <P>See <A 
            href="http://www.mathworks.de/products/filterdesign/demos.html?file=/products/demos/shipping/filterdesign/mfiltcicdecimdemo.html">Using 
            a Cascaded Integrator-Comb (CIC) Decimation Filter</A> for a demo of 
            CICs. </P>
            <P>The design and cascade of the three filters can be performed via 
            the graphical user interface FDATool,</P>
            <P><A 
            onmouseover="window.status='Click to enlarge image.'; return true;" 
            onclick="openWindow('/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcdemofdatool.png',778,624, 'scrollbars=no,resizable=yes,status=no'); return false;" 
            onmouseout="window.status='';" 
            href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcdemofdatool.png"><IMG 
            height=280 hspace=5 
            src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcdemofdatool_thumbnail.png" 
            width=350 vspace=5></A> </P>
            <P>but we'll use the command line functionality.</P>
            <P>To avoid quantizing the fixed-point data coming from the mixer, 
            which has a word length of 20 bits and a fractional length of 18 
            bits, (S20,18), we'll set the input word length and fractional 
            length of the CIC to the same values, S20,18. We must also define 
            the word lengths per section of the CIC. These values are chosen to 
            avoid overflow between sections. We define the CIC as follows: </P><PRE class=code>R    = 64; <SPAN class=comment>% Decimation factor</SPAN>
D    = 1;  <SPAN class=comment>% Differential delay</SPAN>
Nsecs= 5;  <SPAN class=comment>% Number of sections</SPAN>
IWL  = 20; <SPAN class=comment>% Input word length</SPAN>
IFL  = 18; <SPAN class=comment>% Input fraction length</SPAN>
OWL  = 20; <SPAN class=comment>% Output word length</SPAN>

<SPAN class=comment>% If the output wordlength is specified when creating a CIC filter then the</SPAN>
<SPAN class=comment>% "FilterInternals" property is set to "MinWordLengths" automatically.</SPAN>
<SPAN class=comment>% Therefore, the minimum word sizes are used between each section.</SPAN>
hcic = mfilt.cicdecim(R,D,Nsecs,IWL,OWL);
hcic.InputFracLength = IFL;
</PRE>
            <P>We can view the CIC's details by invoking the info method.</P><PRE class=code>info(hcic)
</PRE><PRE class=ans>Discrete-Time FIR Multirate Filter (real)
-----------------------------------------
Filter Structure        : Cascaded Integrator-Comb Decimator
Decimation Factor       : 64
Differential Delay      : 1
Number of Sections      : 5
Stable                  : Yes
Linear Phase            : Yes (Type 2)

Input                   : s20,18
Output                  : s20,-12
Filter Internals        : Minimum Word Lengths
  Integrator Section 1  : s49,17
  Integrator Section 2  : s43,11
  Integrator Section 3  : s37,5
  Integrator Section 4  : s33,1
  Integrator Section 5  : s28,-4
  Comb Section 1        : s26,-6
  Comb Section 2        : s25,-7
  Comb Section 3        : s24,-8
  Comb Section 4        : s23,-9
  Comb Section 5        : s23,-9
</PRE>
            <P>Let's plot and analyze the theoretical magnitude response of the 
            CIC filter which will operate at the input rate of 69.333 MHz. </P><PRE class=code>Fs_in = 69.333e6;
h = fvtool(hcic,<SPAN class=string>'Fs'</SPAN>,Fs_in);
set(gcf, <SPAN class=string>'Color'</SPAN>, <SPAN class=string>'White'</SPAN>);
</PRE><A 
            onmouseover="window.status='Click to enlarge image.'; return true;" 
            onclick="openWindow('/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_01.png',600,419, 'scrollbars=no,resizable=yes,status=no'); return false;" 
            onmouseout="window.status='';" 
            href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_01.png"><IMG 
            height=244 hspace=5 
            src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcfilterchaindemo_01_thumbnail.png" 
            width=350 vspace=5></A> 
            <P>The first thing to note is that the CIC filter has a huge 
            passband gain, which is due to the additions and feedback within the 
            structure. We can normalize the CIC's magnitude response by 
            cascading the CIC with a gain that is the inverse of the gain of the 
            CIC. Normalizing the CIC filter response to have 0 dB gain at DC 
            will make it easier to analyze the overlaid filter response of the 
            next stage filter. Note that we will use the CIC before 
            normalization for code generation. </P><PRE class=code>hgain = dfilt.scalar(1/gain(hcic)); <SPAN class=comment>% Define gain</SPAN>
hcicnorm = cascade(hgain,hcic);

<SPAN class=comment>% Replace the CIC in FVTool with a normalized CIC.</SPAN>