uhf_ddc_tb.vhd

用于数字下变频器的 FPGA 实现

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-- Company: 
-- Engineer:
--
-- Create Date:   13:23:05 11/12/2008
-- Design Name:   UHF_ddc
-- Module Name:   D:/ise_fpga/project_UHF_ddc/UHF_ddc_tb.vhd
-- Project Name:  project_UHF_ddc
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: UHF_ddc
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY UHF_ddc_tb_vhd IS
END UHF_ddc_tb_vhd;

ARCHITECTURE behavior OF UHF_ddc_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT UHF_ddc
	PORT(
		clk : IN std_logic;
		aclr : IN std_logic;
		AD_din : IN std_logic_vector(13 downto 0);          
		t_sine				: out std_logic_vector(13 downto 0);
		t_re_multiplier_dout : out std_logic_vector(27 downto 0);		
		t_cic_dout : OUT std_logic_vector(39 downto 0);
		t_cic_dout_rd : OUT std_logic;
		t_cic_rfd : OUT std_logic;
		t_hc_fir_dout_rd : OUT std_logic;
		t_hc_fir_rfd : OUT std_logic;
		t_hc_fir_dout : OUT std_logic_vector(35 downto 0);
		t_lpf_dout : OUT std_logic_vector(39 downto 0);
		t_lpf_fir_rfd : OUT std_logic;
		t_hc_fir_din		: out std_logic_vector(15 downto 0);
		t_lpf_din			: out std_logic_vector(15 downto 0);		
		re_dout : OUT std_logic_vector(31 downto 0);
		im_dout : OUT std_logic_vector(31 downto 0);
		re_dout_rd : OUT std_logic;
		im_dout_rd : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL aclr :  std_logic := '1';
	SIGNAL AD_din :  std_logic_vector(13 downto 0) := "00110011000011";

	--Outputs
	signal t_sine : std_logic_vector(13 downto 0);			
	signal t_re_multiplier_dout : std_logic_vector(27 downto 0);
	SIGNAL t_cic_dout :  std_logic_vector(39 downto 0);
	SIGNAL t_cic_dout_rd :  std_logic;
	SIGNAL t_cic_rfd :  std_logic;
	SIGNAL t_hc_fir_dout_rd :  std_logic;
	SIGNAL t_hc_fir_rfd :  std_logic;
	SIGNAL t_hc_fir_dout :  std_logic_vector(35 downto 0);
	SIGNAL t_lpf_dout :  std_logic_vector(39 downto 0);
	SIGNAL t_lpf_fir_rfd :  std_logic;
	signal t_hc_fir_din		:  std_logic_vector(15 downto 0);
	signal t_lpf_din			:  std_logic_vector(15 downto 0);	
	
	SIGNAL re_dout :  std_logic_vector(31 downto 0);
	SIGNAL im_dout :  std_logic_vector(31 downto 0);
	SIGNAL re_dout_rd :  std_logic;
	SIGNAL im_dout_rd :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: UHF_ddc PORT MAP(
		clk => clk,
		aclr => aclr,
		AD_din => AD_din,
		t_sine => t_sine,			
		t_re_multiplier_dout => t_re_multiplier_dout,
		t_cic_dout => t_cic_dout,
		t_cic_dout_rd => t_cic_dout_rd,
		t_cic_rfd => t_cic_rfd,
		t_hc_fir_dout_rd => t_hc_fir_dout_rd,
		t_hc_fir_rfd => t_hc_fir_rfd,
		t_hc_fir_dout => t_hc_fir_dout,
		t_lpf_dout => t_lpf_dout,
		t_lpf_fir_rfd => t_lpf_fir_rfd,
		t_hc_fir_din		=> t_hc_fir_din,
		t_lpf_din			=> t_lpf_din,		
		re_dout => re_dout,
		im_dout => im_dout,
		re_dout_rd => re_dout_rd,
		im_dout_rd => im_dout_rd
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		aclr <= '0';
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;
	
	clk <= not clk after 8680 ps;
	
	process
	   begin
			wait for 2000 ps;
			AD_din <= AD_din + 1;
			wait for 15360 ps;
				
		end process;

END;