recv_tb.vhd

用于数字下变频器的 FPGA 实现

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-- Company: 
-- Engineer:
--
-- Create Date:   13:33:57 10/31/2008
-- Design Name:   recv
-- Module Name:   D:/ise_fpga/project_115/recv_tb.vhd
-- Project Name:  project_115
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: recv
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE STD.TEXTIO.ALL;

ENTITY recv_tb_vhd IS
END recv_tb_vhd;

ARCHITECTURE behavior OF recv_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT recv
	PORT(
		clk : IN std_logic;
		AD_clk : IN std_logic;
		aclr : IN std_logic;
		coef : IN std_logic_vector(511 downto 0);
		AD_in : IN std_logic_vector(13 downto 0);          
		corr_dout_I : OUT std_logic_vector(43 downto 0);
		corr_dout_Q : OUT std_logic_vector(43 downto 0);
		corr_dout_rd : OUT std_logic;
		t_DDC_dout_I : OUT std_logic_vector(15 downto 0);
		t_DDC_dout_Q : OUT std_logic_vector(15 downto 0);
		t_DDC_dout_I_rd : OUT std_logic;
		t_DDC_dout_Q_rd : OUT std_logic;
		t_re_lpf_din : OUT std_logic_vector(15 downto 0);
		t_corr_din_I		: out std_logic_vector(34 downto 0);
		t_corr_din_nd		: out std_logic;
		shaped_fir_dout_I : OUT std_logic_vector(34 downto 0);
		shaped_fir_dout_Q : OUT std_logic_vector(34 downto 0);
		shaped_fir_dout_rd : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL aclr :  std_logic := '1';
	SIGNAL clk :  std_logic := '0';
	SIGNAL AD_clk :  std_logic := '0';
	SIGNAL AD_in :  std_logic_vector(13 downto 0) := "00011111010000";
	signal coef	: std_logic_vector(511 downto 0):= "11111111011101110011011100010101001001110001110110101011100100110000011000011101001000110101101111101100110001011100000100001111100000000011110000100011110100110010010000101111000110011110110111010100010100001101101000110001111110001000101100001010110101111110101010100000101001011111001000100100101001111101000100000111000011001011001010001110010111010000000101101001110101100111001111111001100110101001101100000010010110110110010000001101001010111101011101100010011010000100111100101010110001101111001110111101";

	--Outputs
	SIGNAL corr_dout_I :  std_logic_vector(43 downto 0);
	SIGNAL corr_dout_Q :  std_logic_vector(43 downto 0);
	SIGNAL corr_dout_rd :  std_logic;
	SIGNAL t_DDC_dout_I :  std_logic_vector(15 downto 0);
	SIGNAL t_DDC_dout_Q :  std_logic_vector(15 downto 0);
	SIGNAL t_DDC_dout_I_rd :  std_logic;
	SIGNAL t_DDC_dout_Q_rd :  std_logic;
	SIGNAL t_re_lpf_din :  std_logic_vector(15 downto 0);
	signal t_corr_din_I		: std_logic_vector(34 downto 0);
	signal t_corr_din_nd		: std_logic;
	SIGNAL shaped_fir_dout_I :  std_logic_vector(34 downto 0);
	SIGNAL shaped_fir_dout_Q :  std_logic_vector(34 downto 0);
	SIGNAL shaped_fir_dout_rd :  std_logic;

	signal corr_dout_clk	: std_logic;
	
	FILE lpf_din  : TEXT IS out "lpf_din_file.txt";      
	FILE ddc_dout : TEXT IS out "ddc_dout_file.txt";
	FILE shaped_fir_dout : TEXT IS out "shaped_dout_file.txt"; 
	FILE corr_dout : TEXT IS out "corr_file.txt"; 	

BEGIN


	corr_dout_rd <= corr_dout_clk;
	-- Instantiate the Unit Under Test (UUT)
	uut: recv PORT MAP(
		clk => clk,
		AD_clk => AD_clk,
		aclr => aclr,
		coef => coef,
		AD_in => AD_in,
		corr_dout_I => corr_dout_I,
		corr_dout_Q => corr_dout_Q,
		corr_dout_rd => corr_dout_clk,
		t_DDC_dout_I => t_DDC_dout_I,
		t_DDC_dout_Q => t_DDC_dout_Q,
		t_DDC_dout_I_rd => t_DDC_dout_I_rd,
		t_DDC_dout_Q_rd => t_DDC_dout_Q_rd,
		t_re_lpf_din => t_re_lpf_din,
		t_corr_din_I	=>	t_corr_din_I,
		t_corr_din_nd	=> t_corr_din_nd,	
		shaped_fir_dout_I => shaped_fir_dout_I,
		shaped_fir_dout_Q => shaped_fir_dout_Q,
		shaped_fir_dout_rd => shaped_fir_dout_rd
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 2000 ns;
		aclr <= '0'; 
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

   clk <= not clk after 10 ns;
	
	AD_clk <= not AD_clk after 100 ns;
	
	process
	begin
		wait for 100 ns;
		AD_in <= AD_in + 1;
		wait for 100 ns;
	end process;

	
	process(AD_clk)
		variable lpf_din_line			: LINE;
		variable ddc_dout_line			: LINE;
		variable shaped_fir_dout_line			: LINE;
		begin
			if (AD_clk'event and AD_clk = '1') then
				write(lpf_din_line,conv_integer(t_re_lpf_din));
				writeline(lpf_din,lpf_din_line);
				
				write(ddc_dout_line,conv_integer(t_DDC_dout_I));
				writeline(ddc_dout,ddc_dout_line);
				
				write(shaped_fir_dout_line,conv_integer(shaped_fir_dout_I(34 downto 3)));
				writeline(shaped_fir_dout,shaped_fir_dout_line);
				
			end if;
		end process;	
		
	process(corr_dout_clk)
		variable corr_dout_line			: LINE;		
		begin
				if (corr_dout_clk'event and corr_dout_clk = '1') then
					write(corr_dout_line,conv_integer(corr_dout_I(43 downto 12)));
					writeline(corr_dout,corr_dout_line);		
				end if;
		end process;
END;