mw_c28xx_csl.c

由MATLAB生成的AD的源代码

#include "DSP281x_Device.h"
#include "rtwtypes.h"
#include "c2812adcpwmtest.h"
#include "c2812adcpwmtest_private.h"

/* Function: schedulerTimer_ISR() -------------------------------------
 *
 * Abstract:
 *      This function services interrupts posted by scheduler timer
 */

interrupt void schedulerTimer_ISR(void)
{
  rt_OneStep();
}

/*-----------------------------------------------------------------------------
 * void config_schedulerTimer(void)
 *
 * Abstract:
 *      This function configures scheduler timer
 */

void config_schedulerTimer(void)
{
  InitCpuTimers();

  /* Reassign the PIE vector for TINT0 to point to a specific ISR */
  EALLOW;
  PieVectTable.TINT0 = &schedulerTimer_ISR;
  EDIS;

  /* Configure CPU-Timer 0 to interrupt every 0.0001 sec. */
  /* Parameters:  Timer Pointer, CPU Freq in MHz, Period in usec. */
  ConfigCpuTimer(&CpuTimer0, 150, 0.0001 * 1000000);
  StartCpuTimer0();

  /* Enable TINT0 in the PIE: Group 1 interrupt 7 */
  PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
}

void disableWatchdog(void)
{
  int *WatchdogWDCR = (void *) 0x7029;
  asm(" EALLOW ");
  *WatchdogWDCR = 0x0068;
  asm(" EDIS ");
}

/* Function: config_ADC_A ------------------------------
 *
 * Abstract:
 *      Configure ADC_A
 */

void config_ADC_A(uint16_T maxConv, uint16_T adcChselSEQ1Reg, uint16_T
 adcChselSEQ2Reg, uint16_T adcChselSEQ3Reg, uint16_T adcChselSEQ4Reg)
{
  AdcRegs.ADCTRL1.bit.SUSMOD = 0x0;     // Emulation suspend ignored
  AdcRegs.ADCTRL1.bit.ACQ_PS = 0xF;     // Acquisition window size
  AdcRegs.ADCTRL1.bit.CPS = 0x0;        // Core clock pre-scaler
  AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0;   // Start-Stop sequencer mode
  AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3; // Bandgap and reference powered up
  AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x1;   // Core clock divider
  AdcRegs.ADCTRL3.bit.SMODE_SEL = 0;    // Sequential sampling
  AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = maxConv; // Number of conversions in CONV1 when using A and "A and B" module
  AdcRegs.ADCCHSELSEQ1.all = adcChselSEQ1Reg; // Channels for conversion
  AdcRegs.ADCCHSELSEQ2.all = adcChselSEQ2Reg; // Channels for conversion
  AdcRegs.ADCTRL1.bit.SEQ_CASC = 0;     // Dual sequencer mode
}

/* Function: config_PWM_A ------------------------------
 *
 * Abstract:
 *      Configure PWM_A
 */

void config_PWM_A(uint16_T timerPeriod, uint16_T waveformType,
 uint16_T unit1Status, char* unit1Source, uint16_T unit1Value,
 uint16_T unit2Status, char* unit2Source, uint16_T unit2Value,
 uint16_T unit3Status, char* unit3Source, uint16_T unit3Value, uint16_T
 controlLogic,
 uint16_T enableDeadband1, uint16_T enableDeadband2, uint16_T enableDeadband3,
 uint16_T deadbandPrescaler, uint16_T deadbandPeriod, uint16_T timerToADC)
{
  const uint16_T DISABLED=0;

  /* Initalize EVA Timer1 which controls PWM1-PWM6 */
  EvaRegs.T1PR = timerPeriod;           // period
  EvaRegs.T1CMPR = 0x3C00;              // compare
  EvaRegs.T1CNT = 0x0000;               // counter
  EvaRegs.T1CON.all = 0x1042;           // enable; compare enable; default TMODE 
  EvaRegs.T1CON.bit.TMODE = waveformType; // adjust Timer TMODE
  /* Set ADC SOC signal according to user's request */
  EvaRegs.GPTCONA.bit.T1TOADC = timerToADC;
  /* Enable compare for PWM1-PWM6 */
  EvaRegs.CMPR1 = unit1Status ? unit1Value : DISABLED;
  EvaRegs.CMPR2 = unit2Status ? unit2Value : DISABLED;
  EvaRegs.CMPR3 = unit3Status ? unit3Value : DISABLED;
  /* Compare action control: Action that takes place on a compare event */
  EvaRegs.ACTRA.all = controlLogic;
  EvaRegs.DBTCONA.bit.EDBT1 = enableDeadband1;
  EvaRegs.DBTCONA.bit.EDBT2 = enableDeadband2;
  EvaRegs.DBTCONA.bit.EDBT3 = enableDeadband3;
  EvaRegs.DBTCONA.bit.DBT = deadbandPeriod;
  EvaRegs.DBTCONA.bit.DBTPS = deadbandPrescaler;
  EvaRegs.COMCONA.all = 0xA600;
}

/* Function: enable_interrupts -------------------------------
 *
 * Abstract:
 *      Enable required c2800 DSP interrupts
 */

void enable_interrupts()
{
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Enable CPU INT1 - hooked to CPU Timer 0
  IER |= M_INT1;                        // Enable Global INT1 (CPU Interrupt 1)
  EINT;                                 // Enable Global interrupt INTM
}

/* Function: disable_interrupts -------------------------------
 *
 * Abstract:
 *      Disable required c2800 DSP interrupts
 */

void disable_interrupts()
{
  IER &= M_INT1;                        // Disable Global INT1 (CPU Interrupt 1)
  DINT;                                 // Disable Global interrupt INTM
}

/* Function: init_board() -------------------------------------
 *
 * Abstract:
 *      This function initializes the board
 */

void init_board ()
{
  InitSysCtrl();
  /* Perform additional configuration of the XTINF for speed up */
  XintfRegs.XINTCNF2.bit.XTIMCLK = 0;   // XTIMCLK=SYSCLKOUT/1
  XintfRegs.XINTCNF2.bit.CLKOFF = 0;    // XCLKOUT is enabled
  XintfRegs.XINTCNF2.bit.CLKMODE = 0;   // XCLKOUT = XTIMCLK

  // Make sure write buffer is empty before configuring buffering depth
  while(XintfRegs.XINTCNF2.bit.WLEVEL != 0); // poll the WLEVEL bit
  XintfRegs.XINTCNF2.bit.WRBUFF = 0;    // No write buffering

  // Example: Assume Zone 7 is slow, so add additional BCYC cycles whenever
  // switching from Zone 7 to another Zone.  This will help avoid bus contention.
  XintfRegs.XBANK.bit.BCYC = 7;         // Add 7 cycles
  XintfRegs.XBANK.bit.BANK = 7;         // select zone 7

  /* Zone 0 Configuration */
  XintfRegs.XTIMING0.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING0.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING0.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING0.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING0.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING0.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING0.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING0.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING0.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING0.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 1 Configuration */
  XintfRegs.XTIMING1.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING1.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING1.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING1.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING1.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING1.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING1.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING1.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING1.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING1.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 2 Configuration */
  XintfRegs.XTIMING2.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING2.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING2.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING2.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING2.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING2.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING2.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING2.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING2.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING2.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 6 Configuration */
  XintfRegs.XTIMING6.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING6.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING6.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING6.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING6.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING6.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING6.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING6.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING6.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING6.bit.XWRTRAIL = 0; // Write trail time

  /* Zone 7 Configuration */
  XintfRegs.XTIMING7.bit.X2TIMING = 0; // Timing scale factor = 1
  XintfRegs.XTIMING7.bit.XSIZE = 3;     // Always write as 11b
  XintfRegs.XTIMING7.bit.READYMODE = 1; // XREADY is asynchronous
  XintfRegs.XTIMING7.bit.USEREADY = 0; // Disable XREADY
  XintfRegs.XTIMING7.bit.XRDLEAD = 1;   // Read lead time
  XintfRegs.XTIMING7.bit.XRDACTIVE = 2; // Read active time
  XintfRegs.XTIMING7.bit.XRDTRAIL = 0; // Read trail time
  XintfRegs.XTIMING7.bit.XWRLEAD = 1;   // Write lead time
  XintfRegs.XTIMING7.bit.XWRACTIVE = 2; // Write active time
  XintfRegs.XTIMING7.bit.XWRTRAIL = 0; // Write trail time

  /* Flush pipeline to ensure that the write is complete. Wait to be sure. */
  asm(" RPT #6 || NOP");

  /* Disable and clear all CPU interrupts */
  DINT;
  IER = 0x0000;
  IFR = 0x0000;

  InitPieCtrl();
  InitPieVectTable();

  /* initial SPI function.... */

  /* initial SCI function.... */
}