ps7_instance.mhs

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

 PORT S_AXI_HP3_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP3_RDISSUECAP1_EN, DIR = I
 PORT M_AXI_GP1_ARESETN = ps7_axi_interconnect_0_M_AXI_GP1_ARESETN, DIR = O, SIGIS = RST


BEGIN ps7_axi_interconnect
 PARAMETER INSTANCE = ps7_axi_interconnect_0
 PARAMETER HW_VER = 1.00.a
 #BUS_INTERFACE M_AXI_GP0 = ps7_axi_interconnect_0
 PORT M_AXI_GP0_BREADY = ps7_axi_interconnect_0_M_AXI_GP0_BREADY
 PORT M_AXI_GP0_ARVALID = ps7_axi_interconnect_0_M_AXI_GP0_ARVALID
 PORT M_AXI_GP0_AWVALID = ps7_axi_interconnect_0_M_AXI_GP0_AWVALID
 PORT M_AXI_GP0_WVALID = ps7_axi_interconnect_0_M_AXI_GP0_WVALID
 PORT M_AXI_GP0_AWID = ps7_axi_interconnect_0_M_AXI_GP0_AWID
 PORT M_AXI_GP0_RREADY = ps7_axi_interconnect_0_M_AXI_GP0_RREADY
 PORT M_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP0_ARSIZE
 PORT M_AXI_GP0_AWREADY = ps7_axi_interconnect_0_M_AXI_GP0_AWREADY
 PORT M_AXI_GP0_ARID = ps7_axi_interconnect_0_M_AXI_GP0_ARID
 PORT M_AXI_GP0_WID = ps7_axi_interconnect_0_M_AXI_GP0_WID
 PORT M_AXI_GP0_AWBURST = ps7_axi_interconnect_0_M_AXI_GP0_AWBURST
 PORT M_AXI_GP0_ARBURST = ps7_axi_interconnect_0_M_AXI_GP0_ARBURST
 PORT M_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP0_ARLOCK
 PORT M_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP0_AWLOCK
 PORT M_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP0_AWSIZE
 PORT M_AXI_GP0_ARPROT = ps7_axi_interconnect_0_M_AXI_GP0_ARPROT
 PORT M_AXI_GP0_AWPROT = ps7_axi_interconnect_0_M_AXI_GP0_AWPROT
 PORT M_AXI_GP0_ARADDR = ps7_axi_interconnect_0_M_AXI_GP0_ARADDR
 PORT M_AXI_GP0_BID = ps7_axi_interconnect_0_M_AXI_GP0_BID
 PORT M_AXI_GP0_AWADDR = ps7_axi_interconnect_0_M_AXI_GP0_AWADDR
 PORT M_AXI_GP0_WDATA = ps7_axi_interconnect_0_M_AXI_GP0_WDATA
 PORT M_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP0_ARCACHE
 PORT M_AXI_GP0_AWQOS = ps7_axi_interconnect_0_M_AXI_GP0_AWQOS
 PORT M_AXI_GP0_ARLEN = ps7_axi_interconnect_0_M_AXI_GP0_ARLEN
 PORT M_AXI_GP0_ARQOS = ps7_axi_interconnect_0_M_AXI_GP0_ARQOS
 PORT M_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP0_AWCACHE
 PORT M_AXI_GP0_WREADY = ps7_axi_interconnect_0_M_AXI_GP0_WREADY
 PORT M_AXI_GP0_AWLEN = ps7_axi_interconnect_0_M_AXI_GP0_AWLEN
 PORT M_AXI_GP0_WSTRB = ps7_axi_interconnect_0_M_AXI_GP0_WSTRB
 PORT M_AXI_GP0_ACLK = ps7_axi_interconnect_0_M_AXI_GP0_ACLK
 PORT M_AXI_GP0_ARREADY = ps7_axi_interconnect_0_M_AXI_GP0_ARREADY
 PORT M_AXI_GP0_BVALID = ps7_axi_interconnect_0_M_AXI_GP0_BVALID
 PORT M_AXI_GP0_RLAST = ps7_axi_interconnect_0_M_AXI_GP0_RLAST
 PORT M_AXI_GP0_RVALID = ps7_axi_interconnect_0_M_AXI_GP0_RVALID
 PORT M_AXI_GP0_RID = ps7_axi_interconnect_0_M_AXI_GP0_RID
 PORT M_AXI_GP0_BRESP = ps7_axi_interconnect_0_M_AXI_GP0_BRESP
 PORT M_AXI_GP0_RRESP = ps7_axi_interconnect_0_M_AXI_GP0_RRESP
 PORT M_AXI_GP0_RDATA = ps7_axi_interconnect_0_M_AXI_GP0_RDATA
 PORT M_AXI_GP0_WLAST = ps7_axi_interconnect_0_M_AXI_GP0_WLAST
 PORT M_AXI_GP1_BREADY = ps7_axi_interconnect_0_M_AXI_GP1_BREADY
 PORT M_AXI_GP1_ARQOS = ps7_axi_interconnect_0_M_AXI_GP1_ARQOS
 PORT M_AXI_GP1_ARID = ps7_axi_interconnect_0_M_AXI_GP1_ARID
 PORT M_AXI_GP1_WID = ps7_axi_interconnect_0_M_AXI_GP1_WID
 PORT M_AXI_GP1_AWBURST = ps7_axi_interconnect_0_M_AXI_GP1_AWBURST
 PORT M_AXI_GP1_ARBURST = ps7_axi_interconnect_0_M_AXI_GP1_ARBURST
 PORT M_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP1_ARLOCK
 PORT M_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP1_AWLOCK
 PORT M_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP1_AWSIZE
 PORT M_AXI_GP1_ARPROT = ps7_axi_interconnect_0_M_AXI_GP1_ARPROT
 PORT M_AXI_GP1_AWPROT = ps7_axi_interconnect_0_M_AXI_GP1_AWPROT
 PORT M_AXI_GP1_ARADDR = ps7_axi_interconnect_0_M_AXI_GP1_ARADDR
 PORT M_AXI_GP1_BID = ps7_axi_interconnect_0_M_AXI_GP1_BID
 PORT M_AXI_GP1_AWADDR = ps7_axi_interconnect_0_M_AXI_GP1_AWADDR
 PORT M_AXI_GP1_WDATA = ps7_axi_interconnect_0_M_AXI_GP1_WDATA
 PORT M_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP1_ARCACHE
 PORT M_AXI_GP1_ARLEN = ps7_axi_interconnect_0_M_AXI_GP1_ARLEN
 PORT M_AXI_GP1_RLAST = ps7_axi_interconnect_0_M_AXI_GP1_RLAST
 PORT M_AXI_GP1_AWQOS = ps7_axi_interconnect_0_M_AXI_GP1_AWQOS
 PORT M_AXI_GP1_AWREADY = ps7_axi_interconnect_0_M_AXI_GP1_AWREADY
 PORT M_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP1_AWCACHE
 PORT M_AXI_GP1_AWLEN = ps7_axi_interconnect_0_M_AXI_GP1_AWLEN
 PORT M_AXI_GP1_WSTRB = ps7_axi_interconnect_0_M_AXI_GP1_WSTRB
 PORT M_AXI_GP1_WREADY = ps7_axi_interconnect_0_M_AXI_GP1_WREADY
 PORT M_AXI_GP1_ACLK = ps7_axi_interconnect_0_M_AXI_GP1_ACLK
 PORT M_AXI_GP1_ARREADY = ps7_axi_interconnect_0_M_AXI_GP1_ARREADY
 PORT M_AXI_GP1_BVALID = ps7_axi_interconnect_0_M_AXI_GP1_BVALID
 PORT M_AXI_GP1_RVALID = ps7_axi_interconnect_0_M_AXI_GP1_RVALID
 PORT M_AXI_GP1_RDATA = ps7_axi_interconnect_0_M_AXI_GP1_RDATA
 PORT M_AXI_GP1_RID = ps7_axi_interconnect_0_M_AXI_GP1_RID
 PORT M_AXI_GP1_BRESP = ps7_axi_interconnect_0_M_AXI_GP1_BRESP
 PORT M_AXI_GP1_RRESP = ps7_axi_interconnect_0_M_AXI_GP1_RRESP
 PORT M_AXI_GP1_RREADY = ps7_axi_interconnect_0_M_AXI_GP1_RREADY
 PORT M_AXI_GP1_WVALID = ps7_axi_interconnect_0_M_AXI_GP1_WVALID
 PORT M_AXI_GP1_ARVALID = ps7_axi_interconnect_0_M_AXI_GP1_ARVALID
 PORT M_AXI_GP1_AWID = ps7_axi_interconnect_0_M_AXI_GP1_AWID
 PORT M_AXI_GP1_WLAST = ps7_axi_interconnect_0_M_AXI_GP1_WLAST
 PORT M_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP1_ARSIZE
 PORT M_AXI_GP1_AWVALID = ps7_axi_interconnect_0_M_AXI_GP1_AWVALID
 PORT S_AXI_GP1_WREADY = ps7_axi_interconnect_0_S_AXI_GP1_WREADY
 PORT S_AXI_HP0_RVALID = ps7_axi_interconnect_0_S_AXI_HP0_RVALID
 PORT S_AXI_HP1_WREADY = ps7_axi_interconnect_0_S_AXI_HP1_WREADY
 PORT S_AXI_HP2_WREADY = ps7_axi_interconnect_0_S_AXI_HP2_WREADY
 PORT S_AXI_HP3_WREADY = ps7_axi_interconnect_0_S_AXI_HP3_WREADY
 PORT S_AXI_ACP_WREADY = ps7_axi_interconnect_0_S_AXI_ACP_WREADY
 PORT S_AXI_HP0_AWID = ps7_axi_interconnect_0_S_AXI_HP0_AWID
 PORT S_AXI_HP0_WID = ps7_axi_interconnect_0_S_AXI_HP0_WID
 PORT S_AXI_HP0_WDATA = ps7_axi_interconnect_0_S_AXI_HP0_WDATA
 PORT S_AXI_HP0_WSTRB = ps7_axi_interconnect_0_S_AXI_HP0_WSTRB
 PORT S_AXI_HP2_RLAST = ps7_axi_interconnect_0_S_AXI_HP2_RLAST
 PORT S_AXI_HP2_AWREADY = ps7_axi_interconnect_0_S_AXI_HP2_AWREADY
 PORT S_AXI_HP1_RVALID = ps7_axi_interconnect_0_S_AXI_HP1_RVALID
 PORT S_AXI_HP1_RRESP = ps7_axi_interconnect_0_S_AXI_HP1_RRESP
 PORT S_AXI_HP1_AWVALID = ps7_axi_interconnect_0_S_AXI_HP1_AWVALID
 PORT S_AXI_HP1_RREADY = ps7_axi_interconnect_0_S_AXI_HP1_RREADY
 PORT S_AXI_HP1_BID = ps7_axi_interconnect_0_S_AXI_HP1_BID
 PORT S_AXI_HP1_WLAST = ps7_axi_interconnect_0_S_AXI_HP1_WLAST
 PORT S_AXI_HP1_RID = ps7_axi_interconnect_0_S_AXI_HP1_RID
 PORT S_AXI_HP1_RDATA = ps7_axi_interconnect_0_S_AXI_HP1_RDATA
 PORT S_AXI_HP1_ACLK = ps7_axi_interconnect_0_S_AXI_HP1_ACLK
 PORT S_AXI_HP1_ARVALID = ps7_axi_interconnect_0_S_AXI_HP1_ARVALID
 PORT S_AXI_HP1_BREADY = ps7_axi_interconnect_0_S_AXI_HP1_BREADY
 PORT S_AXI_HP1_WVALID = ps7_axi_interconnect_0_S_AXI_HP1_WVALID
 PORT S_AXI_HP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP1_ARSIZE
 PORT S_AXI_HP1_ARBURST = ps7_axi_interconnect_0_S_AXI_HP1_ARBURST
 PORT S_AXI_HP2_ARREADY = ps7_axi_interconnect_0_S_AXI_HP2_ARREADY
 PORT S_AXI_HP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP1_ARLOCK
 PORT S_AXI_HP1_AWBURST = ps7_axi_interconnect_0_S_AXI_HP1_AWBURST
 PORT S_AXI_HP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP1_AWLOCK
 PORT S_AXI_HP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP1_AWSIZE
 PORT S_AXI_HP1_ARPROT = ps7_axi_interconnect_0_S_AXI_HP1_ARPROT
 PORT S_AXI_HP1_AWPROT = ps7_axi_interconnect_0_S_AXI_HP1_AWPROT
 PORT S_AXI_HP1_ARADDR = ps7_axi_interconnect_0_S_AXI_HP1_ARADDR
 PORT S_AXI_HP1_AWADDR = ps7_axi_interconnect_0_S_AXI_HP1_AWADDR
 PORT S_AXI_HP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP1_ARCACHE
 PORT S_AXI_HP1_ARLEN = ps7_axi_interconnect_0_S_AXI_HP1_ARLEN
 PORT S_AXI_HP1_ARQOS = ps7_axi_interconnect_0_S_AXI_HP1_ARQOS
 PORT S_AXI_ACP_RREADY = ps7_axi_interconnect_0_S_AXI_ACP_RREADY
 PORT S_AXI_ACP_RID = ps7_axi_interconnect_0_S_AXI_ACP_RID
 PORT S_AXI_ACP_RDATA = ps7_axi_interconnect_0_S_AXI_ACP_RDATA
 PORT S_AXI_ACP_ACLK = ps7_axi_interconnect_0_S_AXI_ACP_ACLK
 PORT S_AXI_ACP_ARVALID = ps7_axi_interconnect_0_S_AXI_ACP_ARVALID
 PORT S_AXI_ACP_BREADY = ps7_axi_interconnect_0_S_AXI_ACP_BREADY
 PORT S_AXI_ACP_WVALID = ps7_axi_interconnect_0_S_AXI_ACP_WVALID
 PORT S_AXI_ACP_AWQOS = ps7_axi_interconnect_0_S_AXI_ACP_AWQOS
 PORT S_AXI_ACP_ARID = ps7_axi_interconnect_0_S_AXI_ACP_ARID
 PORT S_AXI_ACP_ARLEN = ps7_axi_interconnect_0_S_AXI_ACP_ARLEN
 PORT S_AXI_ACP_ARPROT = ps7_axi_interconnect_0_S_AXI_ACP_ARPROT
 PORT S_AXI_ACP_AWID = ps7_axi_interconnect_0_S_AXI_ACP_AWID
 PORT S_AXI_ACP_AWPROT = ps7_axi_interconnect_0_S_AXI_ACP_AWPROT
 PORT S_AXI_ACP_WID = ps7_axi_interconnect_0_S_AXI_ACP_WID
 PORT S_AXI_ACP_ARADDR = ps7_axi_interconnect_0_S_AXI_ACP_ARADDR
 PORT S_AXI_ACP_AWADDR = ps7_axi_interconnect_0_S_AXI_ACP_AWADDR
 PORT S_AXI_ACP_ARCACHE = ps7_axi_interconnect_0_S_AXI_ACP_ARCACHE
 PORT S_AXI_ACP_ARQOS = ps7_axi_interconnect_0_S_AXI_ACP_ARQOS
 PORT S_AXI_ACP_ARBURST = ps7_axi_interconnect_0_S_AXI_ACP_ARBURST
 PORT S_AXI_ACP_AWCACHE = ps7_axi_interconnect_0_S_AXI_ACP_AWCACHE
 PORT S_AXI_ACP_AWBURST = ps7_axi_interconnect_0_S_AXI_ACP_AWBURST
 PORT S_AXI_ACP_AWLEN = ps7_axi_interconnect_0_S_AXI_ACP_AWLEN
 PORT S_AXI_ACP_ARSIZE = ps7_axi_interconnect_0_S_AXI_ACP_ARSIZE
 PORT S_AXI_ACP_ARLOCK = ps7_axi_interconnect_0_S_AXI_ACP_ARLOCK
 PORT S_AXI_ACP_AWLOCK = ps7_axi_interconnect_0_S_AXI_ACP_AWLOCK
 PORT S_AXI_ACP_AWSIZE = ps7_axi_interconnect_0_S_AXI_ACP_AWSIZE
 PORT S_AXI_ACP_ARUSER = ps7_axi_interconnect_0_S_AXI_ACP_ARUSER
 PORT S_AXI_ACP_AWUSER = ps7_axi_interconnect_0_S_AXI_ACP_AWUSER
 PORT S_AXI_ACP_WDATA = ps7_axi_interconnect_0_S_AXI_ACP_WDATA
 PORT S_AXI_ACP_WSTRB = ps7_axi_interconnect_0_S_AXI_ACP_WSTRB
 PORT S_AXI_GP0_RLAST = ps7_axi_interconnect_0_S_AXI_GP0_RLAST
 PORT S_AXI_GP0_BVALID = ps7_axi_interconnect_0_S_AXI_GP0_BVALID
 PORT S_AXI_GP1_RID = ps7_axi_interconnect_0_S_AXI_GP1_RID
 PORT S_AXI_GP1_ACLK = ps7_axi_interconnect_0_S_AXI_GP1_ACLK
 PORT S_AXI_GP1_ARVALID = ps7_axi_interconnect_0_S_AXI_GP1_ARVALID
 PORT S_AXI_GP1_BREADY = ps7_axi_interconnect_0_S_AXI_GP1_BREADY
 PORT S_AXI_GP1_WVALID = ps7_axi_interconnect_0_S_AXI_GP1_WVALID
 PORT S_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP1_ARSIZE
 PORT S_AXI_GP1_ARBURST = ps7_axi_interconnect_0_S_AXI_GP1_ARBURST
 PORT S_AXI_HP0_AWREADY = ps7_axi_interconnect_0_S_AXI_HP0_AWREADY
 PORT S_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP1_ARLOCK
 PORT S_AXI_GP1_AWBURST = ps7_axi_interconnect_0_S_AXI_GP1_AWBURST
 PORT S_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP1_AWLOCK
 PORT S_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP1_AWSIZE
 PORT S_AXI_GP1_ARPROT = ps7_axi_interconnect_0_S_AXI_GP1_ARPROT
 PORT S_AXI_GP1_AWPROT = ps7_axi_interconnect_0_S_AXI_GP1_AWPROT
 PORT S_AXI_GP1_ARADDR = ps7_axi_interconnect_0_S_AXI_GP1_ARADDR
 PORT S_AXI_GP1_AWADDR = ps7_axi_interconnect_0_S_AXI_GP1_AWADDR
 PORT S_AXI_GP1_WDATA = ps7_axi_interconnect_0_S_AXI_GP1_WDATA
 PORT S_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP1_ARCACHE
 PORT S_AXI_GP1_ARQOS = ps7_axi_interconnect_0_S_AXI_GP1_ARQOS
 PORT S_AXI_GP1_ARLEN = ps7_axi_interconnect_0_S_AXI_GP1_ARLEN
 PORT S_AXI_GP1_AWQOS = ps7_axi_interconnect_0_S_AXI_GP1_AWQOS
 PORT S_AXI_HP0_ARREADY = ps7_axi_interconnect_0_S_AXI_HP0_ARREADY
 PORT S_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP1_AWCACHE
 PORT S_AXI_GP1_AWLEN = ps7_axi_interconnect_0_S_AXI_GP1_AWLEN
 PORT S_AXI_GP1_WSTRB = ps7_axi_interconnect_0_S_AXI_GP1_WSTRB
 PORT S_AXI_GP1_ARID = ps7_axi_interconnect_0_S_AXI_GP1_ARID
 PORT S_AXI_GP1_AWID = ps7_axi_interconnect_0_S_AXI_GP1_AWID
 PORT S_AXI_GP1_WID = ps7_axi_interconnect_0_S_AXI_GP1_WID
 PORT S_AXI_HP1_RLAST = ps7_axi_interconnect_0_S_AXI_HP1_RLAST
 PORT S_AXI_HP1_AWREADY = ps7_axi_interconnect_0_S_AXI_HP1_AWREADY
 PORT S_AXI_HP0_RLAST = ps7_axi_interconnect_0_S_AXI_HP0_RLAST
 PORT S_AXI_HP0_BVALID = ps7_axi_interconnect_0_S_AXI_HP0_BVALID
 PORT S_AXI_GP0_ARQOS = ps7_axi_interconnect_0_S_AXI_GP0_ARQOS
 PORT S_AXI_GP0_AWBURST = ps7_axi_interconnect_0_S_AXI_GP0_AWBURST
 PORT S_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP0_AWLOCK
 PORT S_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP0_AWSIZE
 PORT S_AXI_GP0_ARPROT = ps7_axi_interconnect_0_S_AXI_GP0_ARPROT
 PORT S_AXI_GP0_AWPROT = ps7_axi_interconnect_0_S_AXI_GP0_AWPROT
 PORT S_AXI_GP0_ARADDR = ps7_axi_interconnect_0_S_AXI_GP0_ARADDR
 PORT S_AXI_GP0_AWADDR = ps7_axi_interconnect_0_S_AXI_GP0_AWADDR
 PORT S_AXI_GP0_WDATA = ps7_axi_interconnect_0_S_AXI_GP0_WDATA
 PORT S_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP0_ARCACHE
 PORT S_AXI_GP1_BVALID = ps7_axi_interconnect_0_S_AXI_GP1_BVALID
 PORT S_AXI_GP0_ARLEN = ps7_axi_interconnect_0_S_AXI_GP0_ARLEN
 PORT S_AXI_GP0_AWQOS = ps7_axi_interconnect_0_S_AXI_GP0_AWQOS
 PORT S_AXI_GP1_ARREADY = ps7_axi_interconnect_0_S_AXI_GP1_ARREADY
 PORT S_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP0_AWCACHE
 PORT S_AXI_GP0_WSTRB = ps7_axi_interconnect_0_S_AXI_GP0_WSTRB
 PORT S_AXI_GP0_ARID = ps7_axi_interconnect_0_S_AXI_GP0_ARID
 PORT S_AXI_GP0_AWID = ps7_axi_interconnect_0_S_AXI_GP0_AWID
 PORT S_AXI_GP0_WID = ps7_axi_interconnect_0_S_AXI_GP0_WID
 PORT S_AXI_HP0_BRESP = ps7_axi_interconnect_0_S_AXI_HP0_BRESP
 PORT S_AXI_HP0_WREADY = ps7_axi_interconnect_0_S_AXI_HP0_WREADY
 PORT S_AXI_GP1_RVALID = ps7_axi_interconnect_0_S_AXI_GP1_RVALID
 PORT S_AXI_GP1_RRESP = ps7_axi_interconnect_0_S_AXI_GP1_RRESP
 PORT S_AXI_GP1_AWVALID = ps7_axi_interconnect_0_S_AXI_GP1_AWVALID