ps7_instance.mhs

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

 PORT S_AXI_HP0_AWBURST = ps7_axi_interconnect_0_S_AXI_HP0_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP0_AWLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_HP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP0_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP0_ARPROT = ps7_axi_interconnect_0_S_AXI_HP0_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP0_AWPROT = ps7_axi_interconnect_0_S_AXI_HP0_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP0_ARADDR = ps7_axi_interconnect_0_S_AXI_HP0_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP0_AWADDR = ps7_axi_interconnect_0_S_AXI_HP0_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP0_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP0_ARLEN = ps7_axi_interconnect_0_S_AXI_HP0_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP0_ARQOS = ps7_axi_interconnect_0_S_AXI_HP0_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP0_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP0_AWQOS = ps7_axi_interconnect_0_S_AXI_HP0_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP0_AWLEN = ps7_axi_interconnect_0_S_AXI_HP0_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP0_ARID = ps7_axi_interconnect_0_S_AXI_HP0_ARID, DIR = I, VEC = [5:0]
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP1
 PORT S_AXI_HP1_RLAST = ps7_axi_interconnect_0_S_AXI_HP1_RLAST, DIR = O
 PORT S_AXI_HP1_BRESP = ps7_axi_interconnect_0_S_AXI_HP1_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP1_ARREADY = ps7_axi_interconnect_0_S_AXI_HP1_ARREADY, DIR = O
 PORT S_AXI_HP1_AWREADY = ps7_axi_interconnect_0_S_AXI_HP1_AWREADY, DIR = O
 PORT S_AXI_HP1_WREADY = ps7_axi_interconnect_0_S_AXI_HP1_WREADY, DIR = O
 PORT S_AXI_HP1_RVALID = ps7_axi_interconnect_0_S_AXI_HP1_RVALID, DIR = O
 PORT S_AXI_HP1_RRESP = ps7_axi_interconnect_0_S_AXI_HP1_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP1_AWVALID = ps7_axi_interconnect_0_S_AXI_HP1_AWVALID, DIR = I
 PORT S_AXI_HP1_RREADY = ps7_axi_interconnect_0_S_AXI_HP1_RREADY, DIR = I
 PORT S_AXI_HP1_BID = ps7_axi_interconnect_0_S_AXI_HP1_BID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP1_WLAST = ps7_axi_interconnect_0_S_AXI_HP1_WLAST, DIR = I
 PORT S_AXI_HP1_RID = ps7_axi_interconnect_0_S_AXI_HP1_RID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP1_RDATA = ps7_axi_interconnect_0_S_AXI_HP1_RDATA, DIR = O, VEC = [63:0]
 PORT S_AXI_HP1_ACLK = ps7_axi_interconnect_0_S_AXI_HP1_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_HP1_ARVALID = ps7_axi_interconnect_0_S_AXI_HP1_ARVALID, DIR = I
 PORT S_AXI_HP1_BREADY = ps7_axi_interconnect_0_S_AXI_HP1_BREADY, DIR = I
 PORT S_AXI_HP1_WVALID = ps7_axi_interconnect_0_S_AXI_HP1_WVALID, DIR = I
 PORT S_AXI_HP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP1_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP1_ARBURST = ps7_axi_interconnect_0_S_AXI_HP1_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP1_ARLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_HP1_AWBURST = ps7_axi_interconnect_0_S_AXI_HP1_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP1_AWLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_HP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP1_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP1_ARPROT = ps7_axi_interconnect_0_S_AXI_HP1_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP1_AWPROT = ps7_axi_interconnect_0_S_AXI_HP1_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP1_ARADDR = ps7_axi_interconnect_0_S_AXI_HP1_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP1_AWADDR = ps7_axi_interconnect_0_S_AXI_HP1_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP1_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP1_ARLEN = ps7_axi_interconnect_0_S_AXI_HP1_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP1_ARQOS = ps7_axi_interconnect_0_S_AXI_HP1_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP1_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP1_AWQOS = ps7_axi_interconnect_0_S_AXI_HP1_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP1_AWLEN = ps7_axi_interconnect_0_S_AXI_HP1_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP1_ARID = ps7_axi_interconnect_0_S_AXI_HP1_ARID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP1_AWID = ps7_axi_interconnect_0_S_AXI_HP1_AWID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP1_WID = ps7_axi_interconnect_0_S_AXI_HP1_WID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP1_WDATA = ps7_axi_interconnect_0_S_AXI_HP1_WDATA, DIR = I, VEC = [63:0]
 PORT S_AXI_HP1_WSTRB = ps7_axi_interconnect_0_S_AXI_HP1_WSTRB, DIR = I, VEC = [7:0]
 PORT S_AXI_HP1_BVALID = ps7_axi_interconnect_0_S_AXI_HP1_BVALID, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP2
 PORT S_AXI_HP2_ARREADY = ps7_axi_interconnect_0_S_AXI_HP2_ARREADY, DIR = O
 PORT S_AXI_HP2_BVALID = ps7_axi_interconnect_0_S_AXI_HP2_BVALID, DIR = O
 PORT S_AXI_HP2_BRESP = ps7_axi_interconnect_0_S_AXI_HP2_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP2_WREADY = ps7_axi_interconnect_0_S_AXI_HP2_WREADY, DIR = O
 PORT S_AXI_HP2_RLAST = ps7_axi_interconnect_0_S_AXI_HP2_RLAST, DIR = O
 PORT S_AXI_HP2_AWREADY = ps7_axi_interconnect_0_S_AXI_HP2_AWREADY, DIR = O
 PORT S_AXI_HP2_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP2_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP2_ARPROT = ps7_axi_interconnect_0_S_AXI_HP2_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP2_AWPROT = ps7_axi_interconnect_0_S_AXI_HP2_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP2_ARADDR = ps7_axi_interconnect_0_S_AXI_HP2_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP2_AWADDR = ps7_axi_interconnect_0_S_AXI_HP2_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP2_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP2_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP2_ARLEN = ps7_axi_interconnect_0_S_AXI_HP2_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP2_ARQOS = ps7_axi_interconnect_0_S_AXI_HP2_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP2_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP2_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP2_AWQOS = ps7_axi_interconnect_0_S_AXI_HP2_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP2_AWLEN = ps7_axi_interconnect_0_S_AXI_HP2_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP2_ARID = ps7_axi_interconnect_0_S_AXI_HP2_ARID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP2_AWID = ps7_axi_interconnect_0_S_AXI_HP2_AWID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP2_WID = ps7_axi_interconnect_0_S_AXI_HP2_WID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP2_WDATA = ps7_axi_interconnect_0_S_AXI_HP2_WDATA, DIR = I, VEC = [63:0]
 PORT S_AXI_HP2_WSTRB = ps7_axi_interconnect_0_S_AXI_HP2_WSTRB, DIR = I, VEC = [7:0]
 PORT S_AXI_HP2_RVALID = ps7_axi_interconnect_0_S_AXI_HP2_RVALID, DIR = O
 PORT S_AXI_HP2_RRESP = ps7_axi_interconnect_0_S_AXI_HP2_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP2_AWVALID = ps7_axi_interconnect_0_S_AXI_HP2_AWVALID, DIR = I
 PORT S_AXI_HP2_RREADY = ps7_axi_interconnect_0_S_AXI_HP2_RREADY, DIR = I
 PORT S_AXI_HP2_BID = ps7_axi_interconnect_0_S_AXI_HP2_BID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP2_WLAST = ps7_axi_interconnect_0_S_AXI_HP2_WLAST, DIR = I
 PORT S_AXI_HP2_RID = ps7_axi_interconnect_0_S_AXI_HP2_RID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP2_RDATA = ps7_axi_interconnect_0_S_AXI_HP2_RDATA, DIR = O, VEC = [63:0]
 PORT S_AXI_HP2_ACLK = ps7_axi_interconnect_0_S_AXI_HP2_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_HP2_ARVALID = ps7_axi_interconnect_0_S_AXI_HP2_ARVALID, DIR = I
 PORT S_AXI_HP2_BREADY = ps7_axi_interconnect_0_S_AXI_HP2_BREADY, DIR = I
 PORT S_AXI_HP2_WVALID = ps7_axi_interconnect_0_S_AXI_HP2_WVALID, DIR = I
 PORT S_AXI_HP2_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP2_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP2_ARBURST = ps7_axi_interconnect_0_S_AXI_HP2_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP2_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP2_ARLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_HP2_AWBURST = ps7_axi_interconnect_0_S_AXI_HP2_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP2_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP2_AWLOCK, DIR = I, VEC = [1:0]
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP3
 PORT S_AXI_HP3_ARREADY = ps7_axi_interconnect_0_S_AXI_HP3_ARREADY, DIR = O
 PORT S_AXI_HP3_WREADY = ps7_axi_interconnect_0_S_AXI_HP3_WREADY, DIR = O
 PORT S_AXI_HP3_BVALID = ps7_axi_interconnect_0_S_AXI_HP3_BVALID, DIR = O
 PORT S_AXI_HP3_BRESP = ps7_axi_interconnect_0_S_AXI_HP3_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP3_RVALID = ps7_axi_interconnect_0_S_AXI_HP3_RVALID, DIR = O
 PORT S_AXI_HP3_RRESP = ps7_axi_interconnect_0_S_AXI_HP3_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP3_AWVALID = ps7_axi_interconnect_0_S_AXI_HP3_AWVALID, DIR = I
 PORT S_AXI_HP3_RREADY = ps7_axi_interconnect_0_S_AXI_HP3_RREADY, DIR = I
 PORT S_AXI_HP3_BID = ps7_axi_interconnect_0_S_AXI_HP3_BID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP3_WLAST = ps7_axi_interconnect_0_S_AXI_HP3_WLAST, DIR = I
 PORT S_AXI_HP3_RID = ps7_axi_interconnect_0_S_AXI_HP3_RID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP3_RDATA = ps7_axi_interconnect_0_S_AXI_HP3_RDATA, DIR = O, VEC = [63:0]
 PORT S_AXI_HP3_ACLK = ps7_axi_interconnect_0_S_AXI_HP3_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_HP3_ARVALID = ps7_axi_interconnect_0_S_AXI_HP3_ARVALID, DIR = I
 PORT S_AXI_HP3_BREADY = ps7_axi_interconnect_0_S_AXI_HP3_BREADY, DIR = I
 PORT S_AXI_HP3_WVALID = ps7_axi_interconnect_0_S_AXI_HP3_WVALID, DIR = I
 PORT S_AXI_HP3_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP3_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP3_ARBURST = ps7_axi_interconnect_0_S_AXI_HP3_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP3_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP3_ARLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_HP3_AWBURST = ps7_axi_interconnect_0_S_AXI_HP3_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP3_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP3_AWLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_HP3_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP3_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP3_ARPROT = ps7_axi_interconnect_0_S_AXI_HP3_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP3_AWPROT = ps7_axi_interconnect_0_S_AXI_HP3_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_HP3_ARADDR = ps7_axi_interconnect_0_S_AXI_HP3_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP3_AWADDR = ps7_axi_interconnect_0_S_AXI_HP3_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_HP3_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP3_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP3_ARLEN = ps7_axi_interconnect_0_S_AXI_HP3_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP3_ARQOS = ps7_axi_interconnect_0_S_AXI_HP3_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP3_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP3_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_HP3_AWQOS = ps7_axi_interconnect_0_S_AXI_HP3_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_HP3_AWLEN = ps7_axi_interconnect_0_S_AXI_HP3_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_HP3_ARID = ps7_axi_interconnect_0_S_AXI_HP3_ARID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP3_AWID = ps7_axi_interconnect_0_S_AXI_HP3_AWID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP3_WID = ps7_axi_interconnect_0_S_AXI_HP3_WID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP3_WDATA = ps7_axi_interconnect_0_S_AXI_HP3_WDATA, DIR = I, VEC = [63:0]
 PORT S_AXI_HP3_WSTRB = ps7_axi_interconnect_0_S_AXI_HP3_WSTRB, DIR = I, VEC = [7:0]
 PORT S_AXI_HP3_RLAST = ps7_axi_interconnect_0_S_AXI_HP3_RLAST, DIR = O
 PORT S_AXI_HP3_AWREADY = ps7_axi_interconnect_0_S_AXI_HP3_AWREADY, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_ACP
 PORT S_AXI_ACP_BVALID = ps7_axi_interconnect_0_S_AXI_ACP_BVALID, DIR = O
 PORT S_AXI_ACP_BRESP = ps7_axi_interconnect_0_S_AXI_ACP_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_ACP_AWREADY = ps7_axi_interconnect_0_S_AXI_ACP_AWREADY, DIR = O
 PORT S_AXI_ACP_RVALID = ps7_axi_interconnect_0_S_AXI_ACP_RVALID, DIR = O
 PORT S_AXI_ACP_WLAST = ps7_axi_interconnect_0_S_AXI_ACP_WLAST, DIR = I
 PORT S_AXI_ACP_RRESP = ps7_axi_interconnect_0_S_AXI_ACP_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_ACP_BID = ps7_axi_interconnect_0_S_AXI_ACP_BID, DIR = O, VEC = [2:0]
 PORT S_AXI_ACP_AWVALID = ps7_axi_interconnect_0_S_AXI_ACP_AWVALID, DIR = I
 PORT S_AXI_ACP_WREADY = ps7_axi_interconnect_0_S_AXI_ACP_WREADY, DIR = O
 PORT S_AXI_ACP_RREADY = ps7_axi_interconnect_0_S_AXI_ACP_RREADY, DIR = I
 PORT S_AXI_ACP_RID = ps7_axi_interconnect_0_S_AXI_ACP_RID, DIR = O, VEC = [2:0]
 PORT S_AXI_ACP_RDATA = ps7_axi_interconnect_0_S_AXI_ACP_RDATA, DIR = O, VEC = [63:0]
 PORT S_AXI_ACP_ACLK = ps7_axi_interconnect_0_S_AXI_ACP_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_ACP_ARVALID = ps7_axi_interconnect_0_S_AXI_ACP_ARVALID, DIR = I
 PORT S_AXI_ACP_BREADY = ps7_axi_interconnect_0_S_AXI_ACP_BREADY, DIR = I
 PORT S_AXI_ACP_WVALID = ps7_axi_interconnect_0_S_AXI_ACP_WVALID, DIR = I
 PORT S_AXI_ACP_AWQOS = ps7_axi_interconnect_0_S_AXI_ACP_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_ACP_ARID = ps7_axi_interconnect_0_S_AXI_ACP_ARID, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_ARLEN = ps7_axi_interconnect_0_S_AXI_ACP_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_ACP_ARPROT = ps7_axi_interconnect_0_S_AXI_ACP_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_AWID = ps7_axi_interconnect_0_S_AXI_ACP_AWID, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_AWPROT = ps7_axi_interconnect_0_S_AXI_ACP_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_WID = ps7_axi_interconnect_0_S_AXI_ACP_WID, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_ARADDR = ps7_axi_interconnect_0_S_AXI_ACP_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_ACP_AWADDR = ps7_axi_interconnect_0_S_AXI_ACP_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_ACP_ARCACHE = ps7_axi_interconnect_0_S_AXI_ACP_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_ACP_ARQOS = ps7_axi_interconnect_0_S_AXI_ACP_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_ACP_ARBURST = ps7_axi_interconnect_0_S_AXI_ACP_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_ACP_AWCACHE = ps7_axi_interconnect_0_S_AXI_ACP_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_ACP_AWBURST = ps7_axi_interconnect_0_S_AXI_ACP_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_ACP_AWLEN = ps7_axi_interconnect_0_S_AXI_ACP_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_ACP_ARSIZE = ps7_axi_interconnect_0_S_AXI_ACP_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_ARLOCK = ps7_axi_interconnect_0_S_AXI_ACP_ARLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_ACP_AWLOCK = ps7_axi_interconnect_0_S_AXI_ACP_AWLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_ACP_AWSIZE = ps7_axi_interconnect_0_S_AXI_ACP_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_ACP_ARUSER = ps7_axi_interconnect_0_S_AXI_ACP_ARUSER, DIR = I, VEC = [4:0]
 PORT S_AXI_ACP_AWUSER = ps7_axi_interconnect_0_S_AXI_ACP_AWUSER, DIR = I, VEC = [4:0]
 PORT S_AXI_ACP_WDATA = ps7_axi_interconnect_0_S_AXI_ACP_WDATA, DIR = I, VEC = [63:0]
 PORT S_AXI_ACP_WSTRB = ps7_axi_interconnect_0_S_AXI_ACP_WSTRB, DIR = I, VEC = [7:0]
 PORT S_AXI_ACP_RLAST = ps7_axi_interconnect_0_S_AXI_ACP_RLAST, DIR = O
 PORT S_AXI_ACP_ARREADY = ps7_axi_interconnect_0_S_AXI_ACP_ARREADY, DIR = O
# RESTET Pins
 PORT M_AXI_GP0_ARESETN = ps7_axi_interconnect_0_M_AXI_GP0_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_HP0_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP0_WRISSUECAP1_EN, DIR = I
 PORT S_AXI_GP1_ARESETN = ps7_axi_interconnect_0_S_AXI_GP1_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_GP0_ARESETN = ps7_axi_interconnect_0_S_AXI_GP0_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_ACP_ARESETN = ps7_axi_interconnect_0_S_AXI_ACP_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_HP0_ARESETN = ps7_axi_interconnect_0_S_AXI_HP0_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_HP0_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP0_RCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP0_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP0_WCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP0_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP0_RACOUNT, DIR = O, VEC = [2:0]
 PORT S_AXI_HP0_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP0_WACOUNT, DIR = O, VEC = [5:0]
 PORT S_AXI_HP0_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP0_RDISSUECAP1_EN, DIR = I
 PORT S_AXI_HP1_ARESETN = ps7_axi_interconnect_0_S_AXI_HP1_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_HP1_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP1_WRISSUECAP1_EN, DIR = I
 PORT S_AXI_HP1_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP1_RCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP1_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP1_WCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP1_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP1_RACOUNT, DIR = O, VEC = [2:0]
 PORT S_AXI_HP1_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP1_WACOUNT, DIR = O, VEC = [5:0]
 PORT S_AXI_HP1_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP1_RDISSUECAP1_EN, DIR = I
 PORT S_AXI_HP2_ARESETN = ps7_axi_interconnect_0_S_AXI_HP2_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_HP2_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP2_WRISSUECAP1_EN, DIR = I
 PORT S_AXI_HP2_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP2_RCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP2_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP2_WCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP2_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP2_RACOUNT, DIR = O, VEC = [2:0]
 PORT S_AXI_HP2_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP2_WACOUNT, DIR = O, VEC = [5:0]
 PORT S_AXI_HP2_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP2_RDISSUECAP1_EN, DIR = I
 PORT S_AXI_HP3_ARESETN = ps7_axi_interconnect_0_S_AXI_HP3_ARESETN, DIR = O, SIGIS = RST
 PORT S_AXI_HP3_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP3_WRISSUECAP1_EN, DIR = I
 PORT S_AXI_HP3_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP3_RCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP3_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP3_WCOUNT, DIR = O, VEC = [7:0]
 PORT S_AXI_HP3_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP3_RACOUNT, DIR = O, VEC = [2:0]
 PORT S_AXI_HP3_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP3_WACOUNT, DIR = O, VEC = [5:0]