ps7_instance.mhs

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

# ##############################################################################
# This is complete Pele System mhs file with tags on it
# Manually created PS7 Internal peripherals for ps7 instance mhs generation
# Tue Aug  9 17:37:48 2011
# Target Board:  xilinx.com ml605 Rev D
# Family:   zynq
# Speed Grade:  -1
# ##############################################################################
PARAMETER VERSION = 2.1.0


PORT IRQ_F2P    =  ps7_IRQ_F2P    , VEC=[15:0], DIR = I
PORT Core0_nFIQ =  ps7_Core0_nFIQ , DIR = I
PORT Core0_nIRQ =  ps7_Core0_nIRQ , DIR = I
PORT Core1_nFIQ =  ps7_Core1_nFIQ , DIR = I
PORT Core1_nIRQ =  ps7_Core1_nIRQ , DIR = I

# TAG_NO__START PCW::MPD::PS7::C_USE_CAN0
 PORT ps7_can_0_CAN_PHY_RX_pin = ps7_can_0_CAN_PHY_RX, DIR = I
 PORT ps7_can_0_CAN_PHY_TX_pin = ps7_can_0_CAN_PHY_TX, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_M_AXI_GP0
 PORT M_AXI_GP0_BREADY = ps7_axi_interconnect_0_M_AXI_GP0_BREADY, DIR = O
 PORT M_AXI_GP0_ARVALID = ps7_axi_interconnect_0_M_AXI_GP0_ARVALID, DIR = O
 PORT M_AXI_GP0_AWVALID = ps7_axi_interconnect_0_M_AXI_GP0_AWVALID, DIR = O
 PORT M_AXI_GP0_WVALID = ps7_axi_interconnect_0_M_AXI_GP0_WVALID, DIR = O
 PORT M_AXI_GP0_AWID = ps7_axi_interconnect_0_M_AXI_GP0_AWID, DIR = O, VEC = [31:0]
 PORT M_AXI_GP0_RREADY = ps7_axi_interconnect_0_M_AXI_GP0_RREADY, DIR = O
 PORT M_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP0_ARSIZE, DIR = O, VEC = [2:0]
 PORT M_AXI_GP0_AWREADY = ps7_axi_interconnect_0_M_AXI_GP0_AWREADY, DIR = I
 PORT M_AXI_GP0_ARID = ps7_axi_interconnect_0_M_AXI_GP0_ARID, DIR = O, VEC = [31:0]
 PORT M_AXI_GP0_WID = ps7_axi_interconnect_0_M_AXI_GP0_WID, DIR = O, VEC = [31:0]
 PORT M_AXI_GP0_AWBURST = ps7_axi_interconnect_0_M_AXI_GP0_AWBURST, DIR = O, VEC = [1:0]
 PORT M_AXI_GP0_ARBURST = ps7_axi_interconnect_0_M_AXI_GP0_ARBURST, DIR = O, VEC = [1:0]
 PORT M_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP0_ARLOCK, DIR = O, VEC = [1:0]
 PORT M_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP0_AWLOCK, DIR = O, VEC = [1:0]
 PORT M_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP0_AWSIZE, DIR = O, VEC = [2:0]
 PORT M_AXI_GP0_ARPROT = ps7_axi_interconnect_0_M_AXI_GP0_ARPROT, DIR = O, VEC = [2:0]
 PORT M_AXI_GP0_AWPROT = ps7_axi_interconnect_0_M_AXI_GP0_AWPROT, DIR = O, VEC = [2:0]
 PORT M_AXI_GP0_ARADDR = ps7_axi_interconnect_0_M_AXI_GP0_ARADDR, DIR = O, VEC = [31:0]
 PORT M_AXI_GP0_BID = ps7_axi_interconnect_0_M_AXI_GP0_BID, DIR = I, VEC = [31:0]
 PORT M_AXI_GP0_AWADDR = ps7_axi_interconnect_0_M_AXI_GP0_AWADDR, DIR = O, VEC = [31:0]
 PORT M_AXI_GP0_WDATA = ps7_axi_interconnect_0_M_AXI_GP0_WDATA, DIR = O, VEC = [31:0]
 PORT M_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP0_ARCACHE, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_AWQOS = ps7_axi_interconnect_0_M_AXI_GP0_AWQOS, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_ARLEN = ps7_axi_interconnect_0_M_AXI_GP0_ARLEN, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_ARQOS = ps7_axi_interconnect_0_M_AXI_GP0_ARQOS, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP0_AWCACHE, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_WREADY = ps7_axi_interconnect_0_M_AXI_GP0_WREADY, DIR = I
 PORT M_AXI_GP0_AWLEN = ps7_axi_interconnect_0_M_AXI_GP0_AWLEN, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_WSTRB = ps7_axi_interconnect_0_M_AXI_GP0_WSTRB, DIR = O, VEC = [3:0]
 PORT M_AXI_GP0_ACLK = ps7_axi_interconnect_0_M_AXI_GP0_ACLK, DIR = I, SIGIS = CLK
 PORT M_AXI_GP0_ARREADY = ps7_axi_interconnect_0_M_AXI_GP0_ARREADY, DIR = I
 PORT M_AXI_GP0_BVALID = ps7_axi_interconnect_0_M_AXI_GP0_BVALID, DIR = I
 PORT M_AXI_GP0_RLAST = ps7_axi_interconnect_0_M_AXI_GP0_RLAST, DIR = I
 PORT M_AXI_GP0_RVALID = ps7_axi_interconnect_0_M_AXI_GP0_RVALID, DIR = I
 PORT M_AXI_GP0_RID = ps7_axi_interconnect_0_M_AXI_GP0_RID, DIR = I, VEC = [31:0]
 PORT M_AXI_GP0_BRESP = ps7_axi_interconnect_0_M_AXI_GP0_BRESP, DIR = I, VEC = [1:0]
 PORT M_AXI_GP0_RRESP = ps7_axi_interconnect_0_M_AXI_GP0_RRESP, DIR = I, VEC = [1:0]
 PORT M_AXI_GP0_RDATA = ps7_axi_interconnect_0_M_AXI_GP0_RDATA, DIR = I, VEC = [31:0]
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_M_AXI_GP1
 PORT M_AXI_GP0_WLAST = ps7_axi_interconnect_0_M_AXI_GP0_WLAST, DIR = O
 PORT M_AXI_GP1_BREADY = ps7_axi_interconnect_0_M_AXI_GP1_BREADY, DIR = O
 PORT M_AXI_GP1_ARQOS = ps7_axi_interconnect_0_M_AXI_GP1_ARQOS, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_ARID = ps7_axi_interconnect_0_M_AXI_GP1_ARID, DIR = O, VEC = [31:0]
 PORT M_AXI_GP1_WID = ps7_axi_interconnect_0_M_AXI_GP1_WID, DIR = O, VEC = [31:0]
 PORT M_AXI_GP1_AWBURST = ps7_axi_interconnect_0_M_AXI_GP1_AWBURST, DIR = O, VEC = [1:0]
 PORT M_AXI_GP1_ARBURST = ps7_axi_interconnect_0_M_AXI_GP1_ARBURST, DIR = O, VEC = [1:0]
 PORT M_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP1_ARLOCK, DIR = O, VEC = [1:0]
 PORT M_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP1_AWLOCK, DIR = O, VEC = [1:0]
 PORT M_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP1_AWSIZE, DIR = O, VEC = [2:0]
 PORT M_AXI_GP1_ARPROT = ps7_axi_interconnect_0_M_AXI_GP1_ARPROT, DIR = O, VEC = [2:0]
 PORT M_AXI_GP1_AWPROT = ps7_axi_interconnect_0_M_AXI_GP1_AWPROT, DIR = O, VEC = [2:0]
 PORT M_AXI_GP1_ARADDR = ps7_axi_interconnect_0_M_AXI_GP1_ARADDR, DIR = O, VEC = [31:0]
 PORT M_AXI_GP1_BID = ps7_axi_interconnect_0_M_AXI_GP1_BID, DIR = I, VEC = [31:0]
 PORT M_AXI_GP1_AWADDR = ps7_axi_interconnect_0_M_AXI_GP1_AWADDR, DIR = O, VEC = [31:0]
 PORT M_AXI_GP1_WDATA = ps7_axi_interconnect_0_M_AXI_GP1_WDATA, DIR = O, VEC = [31:0]
 PORT M_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP1_ARCACHE, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_ARLEN = ps7_axi_interconnect_0_M_AXI_GP1_ARLEN, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_RLAST = ps7_axi_interconnect_0_M_AXI_GP1_RLAST, DIR = I
 PORT M_AXI_GP1_AWQOS = ps7_axi_interconnect_0_M_AXI_GP1_AWQOS, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_AWREADY = ps7_axi_interconnect_0_M_AXI_GP1_AWREADY, DIR = I
 PORT M_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP1_AWCACHE, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_AWLEN = ps7_axi_interconnect_0_M_AXI_GP1_AWLEN, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_WSTRB = ps7_axi_interconnect_0_M_AXI_GP1_WSTRB, DIR = O, VEC = [3:0]
 PORT M_AXI_GP1_WREADY = ps7_axi_interconnect_0_M_AXI_GP1_WREADY, DIR = I
 PORT M_AXI_GP1_ACLK = ps7_axi_interconnect_0_M_AXI_GP1_ACLK, DIR = I, SIGIS = CLK
 PORT M_AXI_GP1_ARREADY = ps7_axi_interconnect_0_M_AXI_GP1_ARREADY, DIR = I
 PORT M_AXI_GP1_BVALID = ps7_axi_interconnect_0_M_AXI_GP1_BVALID, DIR = I
 PORT M_AXI_GP1_RVALID = ps7_axi_interconnect_0_M_AXI_GP1_RVALID, DIR = I
 PORT M_AXI_GP1_RDATA = ps7_axi_interconnect_0_M_AXI_GP1_RDATA, DIR = I, VEC = [31:0]
 PORT M_AXI_GP1_RID = ps7_axi_interconnect_0_M_AXI_GP1_RID, DIR = I, VEC = [31:0]
 PORT M_AXI_GP1_BRESP = ps7_axi_interconnect_0_M_AXI_GP1_BRESP, DIR = I, VEC = [1:0]
 PORT M_AXI_GP1_RRESP = ps7_axi_interconnect_0_M_AXI_GP1_RRESP, DIR = I, VEC = [1:0]
 PORT M_AXI_GP1_RREADY = ps7_axi_interconnect_0_M_AXI_GP1_RREADY, DIR = O
 PORT M_AXI_GP1_WVALID = ps7_axi_interconnect_0_M_AXI_GP1_WVALID, DIR = O
 PORT M_AXI_GP1_ARVALID = ps7_axi_interconnect_0_M_AXI_GP1_ARVALID, DIR = O
 PORT M_AXI_GP1_AWID = ps7_axi_interconnect_0_M_AXI_GP1_AWID, DIR = O, VEC = [31:0]
 PORT M_AXI_GP1_WLAST = ps7_axi_interconnect_0_M_AXI_GP1_WLAST, DIR = O
 PORT M_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP1_ARSIZE, DIR = O, VEC = [2:0]
 PORT M_AXI_GP1_AWVALID = ps7_axi_interconnect_0_M_AXI_GP1_AWVALID, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_GP0
 PORT S_AXI_GP0_RLAST = ps7_axi_interconnect_0_S_AXI_GP0_RLAST, DIR = O
 PORT S_AXI_GP0_BVALID = ps7_axi_interconnect_0_S_AXI_GP0_BVALID, DIR = O
 PORT S_AXI_GP0_ARQOS = ps7_axi_interconnect_0_S_AXI_GP0_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_AWBURST = ps7_axi_interconnect_0_S_AXI_GP0_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP0_AWLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP0_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_GP0_ARPROT = ps7_axi_interconnect_0_S_AXI_GP0_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_GP0_AWPROT = ps7_axi_interconnect_0_S_AXI_GP0_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_GP0_ARADDR = ps7_axi_interconnect_0_S_AXI_GP0_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_GP0_AWADDR = ps7_axi_interconnect_0_S_AXI_GP0_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_GP0_WDATA = ps7_axi_interconnect_0_S_AXI_GP0_WDATA, DIR = I, VEC = [31:0]
 PORT S_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP0_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_ARLEN = ps7_axi_interconnect_0_S_AXI_GP0_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_AWQOS = ps7_axi_interconnect_0_S_AXI_GP0_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP0_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_WSTRB = ps7_axi_interconnect_0_S_AXI_GP0_WSTRB, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_ARID = ps7_axi_interconnect_0_S_AXI_GP0_ARID, DIR = I, VEC = [31:0]
 PORT S_AXI_GP0_AWID = ps7_axi_interconnect_0_S_AXI_GP0_AWID, DIR = I, VEC = [31:0]
 PORT S_AXI_GP0_WID = ps7_axi_interconnect_0_S_AXI_GP0_WID, DIR = I, VEC = [31:0]
 PORT S_AXI_GP0_AWREADY = ps7_axi_interconnect_0_S_AXI_GP0_AWREADY, DIR = O
 PORT S_AXI_GP0_BRESP = ps7_axi_interconnect_0_S_AXI_GP0_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_GP0_ARREADY = ps7_axi_interconnect_0_S_AXI_GP0_ARREADY, DIR = O
 PORT S_AXI_GP0_RVALID = ps7_axi_interconnect_0_S_AXI_GP0_RVALID, DIR = O
 PORT S_AXI_GP0_RRESP = ps7_axi_interconnect_0_S_AXI_GP0_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_GP0_AWVALID = ps7_axi_interconnect_0_S_AXI_GP0_AWVALID, DIR = I
 PORT S_AXI_GP0_RREADY = ps7_axi_interconnect_0_S_AXI_GP0_RREADY, DIR = I
 PORT S_AXI_GP0_RDATA = ps7_axi_interconnect_0_S_AXI_GP0_RDATA, DIR = O, VEC = [31:0]
 PORT S_AXI_GP0_WLAST = ps7_axi_interconnect_0_S_AXI_GP0_WLAST, DIR = I
 PORT S_AXI_GP0_BID = ps7_axi_interconnect_0_S_AXI_GP0_BID, DIR = O, VEC = [31:0]
 PORT S_AXI_GP0_RID = ps7_axi_interconnect_0_S_AXI_GP0_RID, DIR = O, VEC = [31:0]
 PORT S_AXI_GP0_ACLK = ps7_axi_interconnect_0_S_AXI_GP0_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_GP0_ARVALID = ps7_axi_interconnect_0_S_AXI_GP0_ARVALID, DIR = I
 PORT S_AXI_GP0_BREADY = ps7_axi_interconnect_0_S_AXI_GP0_BREADY, DIR = I
 PORT S_AXI_GP0_WVALID = ps7_axi_interconnect_0_S_AXI_GP0_WVALID, DIR = I
 PORT S_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP0_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_GP0_AWLEN = ps7_axi_interconnect_0_S_AXI_GP0_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_GP0_ARBURST = ps7_axi_interconnect_0_S_AXI_GP0_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP0_ARLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_GP0_WREADY = ps7_axi_interconnect_0_S_AXI_GP0_WREADY, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_GP1
 PORT S_AXI_GP1_WREADY = ps7_axi_interconnect_0_S_AXI_GP1_WREADY, DIR = O
 PORT S_AXI_GP1_RID = ps7_axi_interconnect_0_S_AXI_GP1_RID, DIR = O, VEC = [2:0]
 PORT S_AXI_GP1_ACLK = ps7_axi_interconnect_0_S_AXI_GP1_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_GP1_ARVALID = ps7_axi_interconnect_0_S_AXI_GP1_ARVALID, DIR = I
 PORT S_AXI_GP1_BREADY = ps7_axi_interconnect_0_S_AXI_GP1_BREADY, DIR = I
 PORT S_AXI_GP1_WVALID = ps7_axi_interconnect_0_S_AXI_GP1_WVALID, DIR = I
 PORT S_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP1_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_GP1_ARBURST = ps7_axi_interconnect_0_S_AXI_GP1_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP1_ARLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_GP1_AWBURST = ps7_axi_interconnect_0_S_AXI_GP1_AWBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP1_AWLOCK, DIR = I, VEC = [1:0]
 PORT S_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP1_AWSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_GP1_ARPROT = ps7_axi_interconnect_0_S_AXI_GP1_ARPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_GP1_AWPROT = ps7_axi_interconnect_0_S_AXI_GP1_AWPROT, DIR = I, VEC = [2:0]
 PORT S_AXI_GP1_ARADDR = ps7_axi_interconnect_0_S_AXI_GP1_ARADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_GP1_AWADDR = ps7_axi_interconnect_0_S_AXI_GP1_AWADDR, DIR = I, VEC = [31:0]
 PORT S_AXI_GP1_WDATA = ps7_axi_interconnect_0_S_AXI_GP1_WDATA, DIR = I, VEC = [31:0]
 PORT S_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP1_ARCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_ARQOS = ps7_axi_interconnect_0_S_AXI_GP1_ARQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_ARLEN = ps7_axi_interconnect_0_S_AXI_GP1_ARLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_AWQOS = ps7_axi_interconnect_0_S_AXI_GP1_AWQOS, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP1_AWCACHE, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_AWLEN = ps7_axi_interconnect_0_S_AXI_GP1_AWLEN, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_WSTRB = ps7_axi_interconnect_0_S_AXI_GP1_WSTRB, DIR = I, VEC = [3:0]
 PORT S_AXI_GP1_ARID = ps7_axi_interconnect_0_S_AXI_GP1_ARID, DIR = I, VEC = [31:0]
 PORT S_AXI_GP1_AWID = ps7_axi_interconnect_0_S_AXI_GP1_AWID, DIR = I, VEC = [31:0]
 PORT S_AXI_GP1_WID = ps7_axi_interconnect_0_S_AXI_GP1_WID, DIR = I, VEC = [31:0]
 PORT S_AXI_GP1_BVALID = ps7_axi_interconnect_0_S_AXI_GP1_BVALID, DIR = O
 PORT S_AXI_GP1_ARREADY = ps7_axi_interconnect_0_S_AXI_GP1_ARREADY, DIR = O
 PORT S_AXI_GP1_RVALID = ps7_axi_interconnect_0_S_AXI_GP1_RVALID, DIR = O
 PORT S_AXI_GP1_RRESP = ps7_axi_interconnect_0_S_AXI_GP1_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_GP1_AWVALID = ps7_axi_interconnect_0_S_AXI_GP1_AWVALID, DIR = I
 PORT S_AXI_GP1_RREADY = ps7_axi_interconnect_0_S_AXI_GP1_RREADY, DIR = I
 PORT S_AXI_GP1_RDATA = ps7_axi_interconnect_0_S_AXI_GP1_RDATA, DIR = O, VEC = [31:0]
 PORT S_AXI_GP1_WLAST = ps7_axi_interconnect_0_S_AXI_GP1_WLAST, DIR = I
 PORT S_AXI_GP1_BID = ps7_axi_interconnect_0_S_AXI_GP1_BID, DIR = O, VEC = [2:0]
 PORT S_AXI_GP1_BRESP = ps7_axi_interconnect_0_S_AXI_GP1_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_GP1_RLAST = ps7_axi_interconnect_0_S_AXI_GP1_RLAST, DIR = O
 PORT S_AXI_GP1_AWREADY = ps7_axi_interconnect_0_S_AXI_GP1_AWREADY, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP0
 PORT S_AXI_HP0_BRESP = ps7_axi_interconnect_0_S_AXI_HP0_BRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP0_WREADY = ps7_axi_interconnect_0_S_AXI_HP0_WREADY, DIR = O
 PORT S_AXI_HP0_RLAST = ps7_axi_interconnect_0_S_AXI_HP0_RLAST, DIR = O
 PORT S_AXI_HP0_BVALID = ps7_axi_interconnect_0_S_AXI_HP0_BVALID, DIR = O
 PORT S_AXI_HP0_AWREADY = ps7_axi_interconnect_0_S_AXI_HP0_AWREADY, DIR = O
 PORT S_AXI_HP0_ARREADY = ps7_axi_interconnect_0_S_AXI_HP0_ARREADY, DIR = O
 PORT S_AXI_HP0_RVALID = ps7_axi_interconnect_0_S_AXI_HP0_RVALID, DIR = O
 PORT S_AXI_HP0_AWID = ps7_axi_interconnect_0_S_AXI_HP0_AWID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP0_WID = ps7_axi_interconnect_0_S_AXI_HP0_WID, DIR = I, VEC = [5:0]
 PORT S_AXI_HP0_WDATA = ps7_axi_interconnect_0_S_AXI_HP0_WDATA, DIR = I, VEC = [63:0]
 PORT S_AXI_HP0_WSTRB = ps7_axi_interconnect_0_S_AXI_HP0_WSTRB, DIR = I, VEC = [7:0]
 PORT S_AXI_HP0_RRESP = ps7_axi_interconnect_0_S_AXI_HP0_RRESP, DIR = O, VEC = [1:0]
 PORT S_AXI_HP0_AWVALID = ps7_axi_interconnect_0_S_AXI_HP0_AWVALID, DIR = I
 PORT S_AXI_HP0_RREADY = ps7_axi_interconnect_0_S_AXI_HP0_RREADY, DIR = I
 PORT S_AXI_HP0_BID = ps7_axi_interconnect_0_S_AXI_HP0_BID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP0_WLAST = ps7_axi_interconnect_0_S_AXI_HP0_WLAST, DIR = I
 PORT S_AXI_HP0_RID = ps7_axi_interconnect_0_S_AXI_HP0_RID, DIR = O, VEC = [5:0]
 PORT S_AXI_HP0_RDATA = ps7_axi_interconnect_0_S_AXI_HP0_RDATA, DIR = O, VEC = [63:0]
 PORT S_AXI_HP0_ACLK = ps7_axi_interconnect_0_S_AXI_HP0_ACLK, DIR = I, SIGIS = CLK
 PORT S_AXI_HP0_ARVALID = ps7_axi_interconnect_0_S_AXI_HP0_ARVALID, DIR = I
 PORT S_AXI_HP0_BREADY = ps7_axi_interconnect_0_S_AXI_HP0_BREADY, DIR = I
 PORT S_AXI_HP0_WVALID = ps7_axi_interconnect_0_S_AXI_HP0_WVALID, DIR = I
 PORT S_AXI_HP0_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP0_ARSIZE, DIR = I, VEC = [2:0]
 PORT S_AXI_HP0_ARBURST = ps7_axi_interconnect_0_S_AXI_HP0_ARBURST, DIR = I, VEC = [1:0]
 PORT S_AXI_HP0_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP0_ARLOCK, DIR = I, VEC = [1:0]