system.xreport

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    <toc-item title="Router Information" target="Starting Router" />
    <toc-item title="Partition Status" target="Partition Implementation Status" />
    <toc-item title="Clock Report" target="Generating Clock Report" />
    <toc-item title="Timing Results" target="Timing Score:" />
    <toc-item title="Final Summary" target="Peak Memory Usage:" />
   </view>
   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="implementation\system.twr" label="Post-PAR Static Timing Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    <toc-item title="Informational Messages" target="INFO:" />
    <toc-item title="Warning Messages" target="WARNING:" />
    <toc-item title="Timing Constraints" target="Timing constraint:" />
    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
    <toc-item title="Timing Summary" target="Timing summary:" />
    <toc-item title="Trace Settings" target="Trace Settings:" />
   </view>
   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.rpt" label="CPLD Fitter Report (Text)" >
    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    <toc-item title="Pin Resources" target="** Pin Resources **" />
    <toc-item title="Global Resources" target="** Global Control Resources **" />
   </view>
   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.tim" label="CPLD Timing Report (Text)" >
    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    <toc-item title="Performance Summary" target="Performance Summary:" />
   </view>
   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="Report" file="implementation\system.pwr" label="Power Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Power summary" target="Power summary" />
    <toc-item title="Thermal summary" target="Thermal summary" />
   </view>
   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="implementation\system.bgn" label="Bitgen Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    <toc-item title="Final Summary" target="DRC detected" />
   </view>
  </viewgroup>
  <viewgroup label="Secondary Reports" >
   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="implementation\isim.log" label="ISIM Simulator Log" />
   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/synthesis/system_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
   </view>
   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/translate/system_translate.nlf" label="Post-Translate Simulation Model Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
   </view>
   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system_map.map" label="Map Log File" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    <toc-item title="Design Information" target="Design Information" />
    <toc-item title="Design Summary" target="Design Summary" />
   </view>
   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.twr" label="Post-Map Static Timing Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    <toc-item title="Informational Messages" target="INFO:" />
    <toc-item title="Warning Messages" target="WARNING:" />
    <toc-item title="Timing Constraints" target="Timing constraint:" />
    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
    <toc-item title="Timing Summary" target="Timing summary:" />
    <toc-item title="Trace Settings" target="Trace Settings:" />
   </view>
   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/map/system_map.nlf" label="Post-Map Simulation Model Report" />
   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_map.psr" label="Physical Synthesis Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
   </view>
   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="implementation\system_pad.txt" label="Pad Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
   </view>
   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system.unroutes" label="Unroutes Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
   </view>
   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
   </view>
   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.grf" label="Guide Results Report" />
   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.dly" label="Asynchronous Delay Report" />
   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.clk_rgn" label="Clock Region Report" />
   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.tsi" label="Post-Place and Route Constraints Interaction Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
   </view>
   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/par/system_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_sta.nlf" label="Primetime Netlist Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
   </view>
   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="implementation\system.ibs" label="IBIS Model" >
    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    <toc-item title="Component" target="Component " />
   </view>
   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lck" label="Back-annotate Pin Report" >
    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
   </view>
   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lpc" label="Locked Pin Constraints" >
    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
   </view>
   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Secondary_Report" file="implementation\netgen/fit/system_timesim.nlf" label="Post-Fit Simulation Model Report" />
   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="implementation\usage_statistics_webtalk.html" label="WebTalk Report" />
   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\webtalk.log" label="WebTalk Log File" />
  </viewgroup>
 </body>
</report-views>