📄 system.xreport
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<?xml version='1.0' encoding='UTF-8'?><report-views version="2.0" > <header> <DateModified>2012-10-08T08:59:25</DateModified> <ModuleName>system</ModuleName> <SummaryTimeStamp>2012-10-08T08:59:25</SummaryTimeStamp> <SavedFilePath>D:/_prj/Xilinx/Blog/Lab3/__xps/ise/system.xreport</SavedFilePath> <FilterFile>filter.filter</FilterFile> <SavedFilterFilePath>D:/_prj/Xilinx/Blog/Lab3/__xps/ise</SavedFilterFilePath> <DateInitialized>2012-10-08T08:59:25</DateInitialized> <EnableMessageFiltering>false</EnableMessageFiltering> </header> <body> <viewgroup label="Design Overview" > <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="implementation\system_summary.html" label="Summary" > <toc-item title="Design Overview" target="Design Overview" /> <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> <toc-item title="Performance Summary" target="Performance Summary" /> <toc-item title="Failing Constraints" target="Failing Constraints" /> <toc-item title="Detailed Reports" target="Detailed Reports" /> </view> <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="implementation\system_envsettings.html" label="System Settings" /> <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="implementation\system_map.xrpt" label="IOB Properties" /> <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="implementation\system_map.xrpt" label="Control Set Information" /> <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="implementation\system_map.xrpt" label="Module Level Utilization" /> <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="implementation\system.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="implementation\system_par.xrpt" label="Pinout Report" /> <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="implementation\system_par.xrpt" label="Clock Report" /> <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="Timing_Analyzer" file="implementation\system.twx" label="Static Timing" /> <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/fit/report.htm" label="CPLD Fitter Report" /> <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/tim/report.htm" label="CPLD Timing Report" /> </viewgroup> <viewgroup label="XPS Errors and Warnings" > <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> </viewgroup> <viewgroup label="XPS Reports" > <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="system.log" label="System Log File" /> </viewgroup> <viewgroup label="Errors and Warnings" > <view program="pn" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered, New" file="implementation\_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="synthesis\_xmsgs/xst.xmsgs" label="Synthesis Messages" /> <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/map.xmsgs" label="Map Messages" /> <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/par.xmsgs" label="Place and Route Messages" /> <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/trce.xmsgs" label="Timing Messages" /> <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/xpwr.xmsgs" label="Power Messages" /> <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/*.xmsgs" label="All Implementation Messages" /> <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="implementation\_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> </viewgroup> <viewgroup label="Detailed Reports" > <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.syr" label="Synthesis Report" > <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> <toc-item title="HDL Compilation" target=" HDL Compilation " /> <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> <toc-item title="HDL Analysis" target=" HDL Analysis " /> <toc-item title="HDL Parsing" target=" HDL Parsing " /> <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> <toc-item title="Partition Report" target=" Partition Report " /> <toc-item title="Final Report" target=" Final Report " /> <toc-item title="Design Summary" target=" Design Summary " /> <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> </view> <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.srr" label="Synplify Report" /> <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.prec_log" label="Precision Report" /> <view inputState="Synthesized" program="ngdbuild" type="Report" file="implementation\system.bld" label="Translation Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> <toc-item title="Command Line" target="Command Line:" /> <toc-item title="Partition Status" target="Partition Implementation Status" /> <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> </view> <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="implementation\system_map.mrp" label="Map Report" > <toc-item title="Top of Report" target="Release" searchDir="Forward" /> <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> </view> <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="implementation\system.par" label="Place and Route Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />⌨️ 快捷键说明
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