system_processing_system7_0_wrapper.v

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

  input S_AXI_HP1_RREADY;
  input S_AXI_HP1_WLAST;
  input S_AXI_HP1_WRISSUECAP1_EN;
  input S_AXI_HP1_WVALID;
  input [1:0] S_AXI_HP1_ARBURST;
  input [1:0] S_AXI_HP1_ARLOCK;
  input [2:0] S_AXI_HP1_ARSIZE;
  input [1:0] S_AXI_HP1_AWBURST;
  input [1:0] S_AXI_HP1_AWLOCK;
  input [2:0] S_AXI_HP1_AWSIZE;
  input [2:0] S_AXI_HP1_ARPROT;
  input [2:0] S_AXI_HP1_AWPROT;
  input [31:0] S_AXI_HP1_ARADDR;
  input [31:0] S_AXI_HP1_AWADDR;
  input [3:0] S_AXI_HP1_ARCACHE;
  input [3:0] S_AXI_HP1_ARLEN;
  input [3:0] S_AXI_HP1_ARQOS;
  input [3:0] S_AXI_HP1_AWCACHE;
  input [3:0] S_AXI_HP1_AWLEN;
  input [3:0] S_AXI_HP1_AWQOS;
  input [5:0] S_AXI_HP1_ARID;
  input [5:0] S_AXI_HP1_AWID;
  input [5:0] S_AXI_HP1_WID;
  input [63:0] S_AXI_HP1_WDATA;
  input [7:0] S_AXI_HP1_WSTRB;
  output S_AXI_HP2_ARESETN;
  output S_AXI_HP2_ARREADY;
  output S_AXI_HP2_AWREADY;
  output S_AXI_HP2_BVALID;
  output S_AXI_HP2_RLAST;
  output S_AXI_HP2_RVALID;
  output S_AXI_HP2_WREADY;
  output [1:0] S_AXI_HP2_BRESP;
  output [1:0] S_AXI_HP2_RRESP;
  output [5:0] S_AXI_HP2_BID;
  output [5:0] S_AXI_HP2_RID;
  output [63:0] S_AXI_HP2_RDATA;
  output [7:0] S_AXI_HP2_RCOUNT;
  output [7:0] S_AXI_HP2_WCOUNT;
  output [2:0] S_AXI_HP2_RACOUNT;
  output [5:0] S_AXI_HP2_WACOUNT;
  input S_AXI_HP2_ACLK;
  input S_AXI_HP2_ARVALID;
  input S_AXI_HP2_AWVALID;
  input S_AXI_HP2_BREADY;
  input S_AXI_HP2_RDISSUECAP1_EN;
  input S_AXI_HP2_RREADY;
  input S_AXI_HP2_WLAST;
  input S_AXI_HP2_WRISSUECAP1_EN;
  input S_AXI_HP2_WVALID;
  input [1:0] S_AXI_HP2_ARBURST;
  input [1:0] S_AXI_HP2_ARLOCK;
  input [2:0] S_AXI_HP2_ARSIZE;
  input [1:0] S_AXI_HP2_AWBURST;
  input [1:0] S_AXI_HP2_AWLOCK;
  input [2:0] S_AXI_HP2_AWSIZE;
  input [2:0] S_AXI_HP2_ARPROT;
  input [2:0] S_AXI_HP2_AWPROT;
  input [31:0] S_AXI_HP2_ARADDR;
  input [31:0] S_AXI_HP2_AWADDR;
  input [3:0] S_AXI_HP2_ARCACHE;
  input [3:0] S_AXI_HP2_ARLEN;
  input [3:0] S_AXI_HP2_ARQOS;
  input [3:0] S_AXI_HP2_AWCACHE;
  input [3:0] S_AXI_HP2_AWLEN;
  input [3:0] S_AXI_HP2_AWQOS;
  input [5:0] S_AXI_HP2_ARID;
  input [5:0] S_AXI_HP2_AWID;
  input [5:0] S_AXI_HP2_WID;
  input [63:0] S_AXI_HP2_WDATA;
  input [7:0] S_AXI_HP2_WSTRB;
  output S_AXI_HP3_ARESETN;
  output S_AXI_HP3_ARREADY;
  output S_AXI_HP3_AWREADY;
  output S_AXI_HP3_BVALID;
  output S_AXI_HP3_RLAST;
  output S_AXI_HP3_RVALID;
  output S_AXI_HP3_WREADY;
  output [1:0] S_AXI_HP3_BRESP;
  output [1:0] S_AXI_HP3_RRESP;
  output [5:0] S_AXI_HP3_BID;
  output [5:0] S_AXI_HP3_RID;
  output [63:0] S_AXI_HP3_RDATA;
  output [7:0] S_AXI_HP3_RCOUNT;
  output [7:0] S_AXI_HP3_WCOUNT;
  output [2:0] S_AXI_HP3_RACOUNT;
  output [5:0] S_AXI_HP3_WACOUNT;
  input S_AXI_HP3_ACLK;
  input S_AXI_HP3_ARVALID;
  input S_AXI_HP3_AWVALID;
  input S_AXI_HP3_BREADY;
  input S_AXI_HP3_RDISSUECAP1_EN;
  input S_AXI_HP3_RREADY;
  input S_AXI_HP3_WLAST;
  input S_AXI_HP3_WRISSUECAP1_EN;
  input S_AXI_HP3_WVALID;
  input [1:0] S_AXI_HP3_ARBURST;
  input [1:0] S_AXI_HP3_ARLOCK;
  input [2:0] S_AXI_HP3_ARSIZE;
  input [1:0] S_AXI_HP3_AWBURST;
  input [1:0] S_AXI_HP3_AWLOCK;
  input [2:0] S_AXI_HP3_AWSIZE;
  input [2:0] S_AXI_HP3_ARPROT;
  input [2:0] S_AXI_HP3_AWPROT;
  input [31:0] S_AXI_HP3_ARADDR;
  input [31:0] S_AXI_HP3_AWADDR;
  input [3:0] S_AXI_HP3_ARCACHE;
  input [3:0] S_AXI_HP3_ARLEN;
  input [3:0] S_AXI_HP3_ARQOS;
  input [3:0] S_AXI_HP3_AWCACHE;
  input [3:0] S_AXI_HP3_AWLEN;
  input [3:0] S_AXI_HP3_AWQOS;
  input [5:0] S_AXI_HP3_ARID;
  input [5:0] S_AXI_HP3_AWID;
  input [5:0] S_AXI_HP3_WID;
  input [63:0] S_AXI_HP3_WDATA;
  input [7:0] S_AXI_HP3_WSTRB;
  output [1:0] DMA0_DATYPE;
  output DMA0_DAVALID;
  output DMA0_DRREADY;
  output DMA0_RSTN;
  input DMA0_ACLK;
  input DMA0_DAREADY;
  input DMA0_DRLAST;
  input DMA0_DRVALID;
  input [1:0] DMA0_DRTYPE;
  output [1:0] DMA1_DATYPE;
  output DMA1_DAVALID;
  output DMA1_DRREADY;
  output DMA1_RSTN;
  input DMA1_ACLK;
  input DMA1_DAREADY;
  input DMA1_DRLAST;
  input DMA1_DRVALID;
  input [1:0] DMA1_DRTYPE;
  output [1:0] DMA2_DATYPE;
  output DMA2_DAVALID;
  output DMA2_DRREADY;
  output DMA2_RSTN;
  input DMA2_ACLK;
  input DMA2_DAREADY;
  input DMA2_DRLAST;
  input DMA2_DRVALID;
  input DMA3_DRVALID;
  output [1:0] DMA3_DATYPE;
  output DMA3_DAVALID;
  output DMA3_DRREADY;
  output DMA3_RSTN;
  input DMA3_ACLK;
  input DMA3_DAREADY;
  input DMA3_DRLAST;
  input [1:0] DMA2_DRTYPE;
  input [1:0] DMA3_DRTYPE;
  input [31:0] FTMD_TRACEIN_DATA;
  input FTMD_TRACEIN_VALID;
  input FTMD_TRACEIN_CLK;
  input [3:0] FTMD_TRACEIN_ATID;
  input [3:0] FTMT_F2P_TRIG;
  output [3:0] FTMT_F2P_TRIGACK;
  input [31:0] FTMT_F2P_DEBUG;
  input [3:0] FTMT_P2F_TRIGACK;
  output [3:0] FTMT_P2F_TRIG;
  output [31:0] FTMT_P2F_DEBUG;
  output FCLK_CLK3;
  output FCLK_CLK2;
  output FCLK_CLK1;
  output FCLK_CLK0;
  input FCLK_CLKTRIG3_N;
  input FCLK_CLKTRIG2_N;
  input FCLK_CLKTRIG1_N;
  input FCLK_CLKTRIG0_N;
  output FCLK_RESET3_N;
  output FCLK_RESET2_N;
  output FCLK_RESET1_N;
  output FCLK_RESET0_N;
  input FPGA_IDLE_N;
  input [3:0] DDR_ARB;
  input [0:0] IRQ_F2P;
  input Core0_nFIQ;
  input Core0_nIRQ;
  input Core1_nFIQ;
  input Core1_nIRQ;
  output EVENT_EVENTO;
  output [1:0] EVENT_STANDBYWFE;
  output [1:0] EVENT_STANDBYWFI;
  input EVENT_EVENTI;
  inout [53:0] MIO;
  inout DDR_Clk;
  inout DDR_Clk_n;
  inout DDR_CKE;
  inout DDR_CS_n;
  inout DDR_RAS_n;
  inout DDR_CAS_n;
  output DDR_WEB;
  inout [2:0] DDR_BankAddr;
  inout [14:0] DDR_Addr;
  inout DDR_ODT;
  inout DDR_DRSTB;
  inout [31:0] DDR_DQ;
  inout [3:0] DDR_DM;
  inout [3:0] DDR_DQS;
  inout [3:0] DDR_DQS_n;
  inout DDR_VRN;
  inout DDR_VRP;
  input PS_SRSTB;
  input PS_CLK;
  input PS_PORB;
  output IRQ_P2F_DMAC_ABORT;
  output IRQ_P2F_DMAC0;
  output IRQ_P2F_DMAC1;
  output IRQ_P2F_DMAC2;
  output IRQ_P2F_DMAC3;
  output IRQ_P2F_DMAC4;
  output IRQ_P2F_DMAC5;
  output IRQ_P2F_DMAC6;
  output IRQ_P2F_DMAC7;
  output IRQ_P2F_SMC;
  output IRQ_P2F_QSPI;
  output IRQ_P2F_CTI;
  output IRQ_P2F_GPIO;
  output IRQ_P2F_USB0;
  output IRQ_P2F_ENET0;
  output IRQ_P2F_ENET_WAKE0;
  output IRQ_P2F_SDIO0;
  output IRQ_P2F_I2C0;
  output IRQ_P2F_SPI0;
  output IRQ_P2F_UART0;
  output IRQ_P2F_CAN0;
  output IRQ_P2F_USB1;
  output IRQ_P2F_ENET1;
  output IRQ_P2F_ENET_WAKE1;
  output IRQ_P2F_SDIO1;
  output IRQ_P2F_I2C1;
  output IRQ_P2F_SPI1;
  output IRQ_P2F_UART1;
  output IRQ_P2F_CAN1;

  (* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_I2C0_PERIPHERAL_ENABLE = 1,C_UART1_PERIPHERAL_ENABLE = 1,C_I2C0_I2C0_IO = MIO 50 .. 51,C_CAN0_CAN0_IO = MIO 46 .. 47,C_CAN0_PERIPHERAL_ENABLE = 1,C_SD0_GRP_CD_IO = MIO 0,C_SD0_GRP_CD_ENABLE = 1,C_TTC0_PERIPHERAL_ENABLE = 1,C_SD0_GRP_WP_IO = MIO 15,C_SD0_GRP_WP_ENABLE = 1,C_SD0_PERIPHERAL_ENABLE = 1,C_ENET0_GRP_MDIO_IO = MIO 52 .. 53,C_ENET0_PERIPHERAL_ENABLE = 1,C_ENET0_ENET0_IO = MIO 16 .. 27,C_ENET0_GRP_MDIO_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_QSPI_GRP_FBCLK_ENABLE = 1,C_USB0_PERIPHERAL_ENABLE = 1,C_WDT_PERIPHERAL_ENABLE = 1,C_PJTAG_PERIPHERAL_ENABLE = 0,C_MIO_MIO[12]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[10]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[8]_PULLUP = disabled,C_MIO_MIO[8]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[6]_PULLUP = disabled,C_MIO_MIO[6]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[5]_SLEW = fast,C_MIO_MIO[4]_PULLUP = disabled,C_MIO_MIO[4]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[3]_SLEW = fast,C_MIO_MIO[2]_PULLUP = disabled,C_MIO_MIO[2]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[1]_SLEW = fast,C_MIO_MIO[0]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[14]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[13]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[11]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[9]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[7]_PULLUP = disabled,C_MIO_MIO[7]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[6]_SLEW = fast,C_MIO_MIO[5]_PULLUP = disabled,C_MIO_MIO[5]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[4]_SLEW = fast,C_MIO_MIO[3]_PULLUP = disabled,C_MIO_MIO[3]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[2]_SLEW = fast,C_MIO_MIO[1]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[0]_SLEW = fast,C_MIO_MIO[31]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[30]_SLEW = fast,C_MIO_MIO[29]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[28]_SLEW = fast,C_MIO_MIO[27]_IOTYPE = HSTL 1.8V,C_MIO_MIO[26]_SLEW = fast,C_MIO_MIO[25]_IOTYPE = HSTL 1.8V,C_MIO_MIO[24]_SLEW = fast,C_MIO_MIO[23]_IOTYPE = HSTL 1.8V,C_MIO_MIO[22]_SLEW = fast,C_MIO_MIO[21]_IOTYPE = HSTL 1.8V,C_MIO_MIO[20]_SLEW = fast,C_MIO_MIO[19]_IOTYPE = HSTL 1.8V,C_MIO_MIO[18]_SLEW = fast,C_MIO_MIO[17]_IOTYPE = HSTL 1.8V,C_MIO_MIO[16]_SLEW = fast,C_MIO_MIO[15]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[31]_SLEW = fast,C_MIO_MIO[30]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[29]_SLEW = fast,C_MIO_MIO[28]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[27]_SLEW = fast,C_MIO_MIO[26]_IOTYPE = HSTL 1.8V,C_MIO_MIO[25]_SLEW = fast,C_MIO_MIO[24]_IOTYPE = HSTL 1.8V,C_MIO_MIO[23]_SLEW = fast,C_MIO_MIO[22]_IOTYPE = HSTL 1.8V,C_MIO_MIO[21]_SLEW = fast,C_MIO_MIO[20]_IOTYPE = HSTL 1.8V,C_MIO_MIO[19]_SLEW = fast,C_MIO_MIO[18]_IOTYPE = HSTL 1.8V,C_MIO_MIO[17]_SLEW = fast,C_MIO_MIO[16]_IOTYPE = HSTL 1.8V,C_MIO_MIO[15]_SLEW = fast,C_MIO_MIO[47]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[44]_SLEW = fast,C_MIO_MIO[43]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[42]_SLEW = fast,C_MIO_MIO[41]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[40]_SLEW = fast,C_MIO_MIO[39]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[38]_SLEW = fast,C_MIO_MIO[37]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[36]_SLEW = fast,C_MIO_MIO[35]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[34]_SLEW = fast,C_MIO_MIO[33]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[32]_SLEW = fast,C_MIO_MIO[46]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_SLEW = fast,C_MIO_MIO[44]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[43]_SLEW = fast,C_MIO_MIO[42]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[41]_SLEW = fast,C_MIO_MIO[40]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[39]_SLEW = fast,C_MIO_MIO[38]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[37]_SLEW = fast,C_MIO_MIO[36]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[35]_SLEW = fast,C_MIO_MIO[34]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[33]_SLEW = fast,C_MIO_MIO[32]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[53]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[51]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[49]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[52]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[50]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[48]_IOTYPE = LVCMOS 1.8V,C_UIPARAM_DDR_PARTNO = MT41J256M8 HX-15E,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 = 0.089,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 = 0.217,C_UIPARAM_DDR_T_FAW = 30.0,C_UIPARAM_DDR_T_RC = 49.5,C_UIPARAM_DDR_T_RCD = 7,C_UIPARAM_DDR_CL = 7,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 = 0.248,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 = 0.133,C_UIPARAM_DDR_T_RAS_MIN = 36.0,C_UIPARAM_DDR_T_RP = 7,C_UIPARAM_DDR_CWL = 6,C_UIPARAM_DDR_FREQ_MHZ = 533.333313,C_UIPARAM_DDR_SPEED_BIN = DDR3_1066F,C_UIPARAM_DDR_DEVICE_CAPACITY = 2048 MBits,C_UIPARAM_DDR_DRAM_WIDTH = 8 Bits,C_UIPARAM_DDR_BL = 8,C_UIPARAM_DDR_MEMORY_TYPE = DDR 3,C_UIPARAM_DDR_BOARD_DELAY2 = 0.464,C_UIPARAM_DDR_BOARD_DELAY0 = 0.537,C_UIPARAM_DDR_USE_INTERNAL_VREF = 1,C_UIPARAM_DDR_TRAIN_READ_GATE = 1,C_UIPARAM_DDR_BOARD_DELAY3 = 0.521,C_UIPARAM_DDR_BOARD_DELAY1 = 0.442,C_UIPARAM_DDR_TRAIN_DATA_EYE = 1,C_UIPARAM_DDR_TRAIN_WRITE_LEVEL = 1,C_GPIO_PERIPHERAL_ENABLE = 1,C_CAN_PERIPHERAL_FREQMHZ = 23.8095,C_UART_PERIPHERAL_FREQMHZ = 50,C_PRESET_GLOBAL_DEFAULT = powerup,C_SDIO_PERIPHERAL_FREQMHZ = 50,C_ENET0_PERIPHERAL_FREQMHZ = 100 Mbps,C_APU_PERIPHERAL_FREQMHZ = 666.666666,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_BANK1_VOLTAGE = LVCMOS 1.8V,C_PSCONFIG_LVL_SHFTR_EN_C_USE_CR_FABRIC = 1,C_PRESET_BANK0_VOLTAGE = LVCMOS 1.8V}" *)

  processing_system7
    #(
      .C_EN_EMIO_ENET0 ( 0 ),
      .C_EN_EMIO_ENET1 ( 0 ),
      .C_EN_EMIO_TRACE ( 0 ),
      .C_INCLUDE_TRACE_BUFFER ( 0 ),
      .C_TRACE_BUFFER_FIFO_SIZE ( 128 ),
      .USE_TRACE_DATA_EDGE_DETECTOR ( 0 ),
      .C_TRACE_BUFFER_CLOCK_DELAY ( 12 ),
      .C_EMIO_GPIO_WIDTH ( 64 ),
      .C_INCLUDE_ACP_TRANS_CHECK ( 0 ),
      .C_USE_DEFAULT_ACP_USER_VAL ( 0 ),
      .C_S_AXI_ACP_ARUSER_VAL ( 31 ),
      .C_S_AXI_ACP_AWUSER_VAL ( 31 ),
      .C_PS7_SI_REV ( "PRODUCTION" ),
      .C_M_AXI_GP0_ID_WIDTH ( 12 ),
      .C_M_AXI_GP0_ENABLE_STATIC_REMAP ( 0 ),
      .C_M_AXI_GP1_ID_WIDTH ( 12 ),
      .C_M_AXI_GP1_ENABLE_STATIC_REMAP ( 0 ),
      .C_S_AXI_GP0_ID_WIDTH ( 6 ),
      .C_S_AXI_GP1_ID_WIDTH ( 6 ),
      .C_S_AXI_ACP_ID_WIDTH ( 3 ),
      .C_S_AXI_HP0_ID_WIDTH ( 6 ),
      .C_S_AXI_HP0_DATA_WIDTH ( 64 ),
      .C_S_AXI_HP1_ID_WIDTH ( 6 ),
      .C_S_AXI_HP1_DATA_WIDTH ( 64 ),
      .C_S_AXI_HP2_ID_WIDTH ( 6 ),
      .C_S_AXI_HP2_DATA_WIDTH ( 64 ),
      .C_S_AXI_HP3_ID_WIDTH ( 6 ),
      .C_S_AXI_HP3_DATA_WIDTH ( 64 ),
      .C_M_AXI_GP0_THREAD_ID_WIDTH ( 12 ),
      .C_M_AXI_GP1_THREAD_ID_WIDTH ( 12 ),
      .C_NUM_F2P_INTR_INPUTS ( 1 ),
      .C_FCLK_CLK0_BUF ( "TRUE" ),
      .C_FCLK_CLK1_BUF ( "FALSE" ),
      .C_FCLK_CLK2_BUF ( "FALSE" ),
      .C_FCLK_CLK3_BUF ( "FALSE" )
    )
    processing_system7_0 (
      .CAN0_PHY_TX ( CAN0_PHY_TX ),
      .CAN0_PHY_RX ( CAN0_PHY_RX ),
      .CAN1_PHY_TX ( CAN1_PHY_TX ),
      .CAN1_PHY_RX ( CAN1_PHY_RX ),
      .ENET0_GMII_TX_EN ( ENET0_GMII_TX_EN ),
      .ENET0_GMII_TX_ER ( ENET0_GMII_TX_ER ),
      .ENET0_MDIO_MDC ( ENET0_MDIO_MDC ),
      .ENET0_MDIO_O ( ENET0_MDIO_O ),
      .ENET0_MDIO_T ( ENET0_MDIO_T ),
      .ENET0_PTP_DELAY_REQ_RX ( ENET0_PTP_DELAY_REQ_RX ),
      .ENET0_PTP_DELAY_REQ_TX ( ENET0_PTP_DELAY_REQ_TX ),
      .ENET0_PTP_PDELAY_REQ_RX ( ENET0_PTP_PDELAY_REQ_RX ),
      .ENET0_PTP_PDELAY_REQ_TX ( ENET0_PTP_PDELAY_REQ_TX ),
      .ENET0_PTP_PDELAY_RESP_RX ( ENET0_PTP_PDELAY_RESP_RX ),
      .ENET0_PTP_PDELAY_RESP_TX ( ENET0_PTP_PDELAY_RESP_TX ),
      .ENET0_PTP_SYNC_FRAME_RX ( ENET0_PTP_SYNC_FRAME_RX ),
      .ENET0_PTP_SYNC_FRAME_TX ( ENET0_PTP_SYNC_FRAME_TX ),
      .ENET0_SOF_RX ( ENET0_SOF_RX ),
      .ENET0_SOF_TX ( ENET0_SOF_TX ),
      .ENET0_GMII_TXD ( ENET0_GMII_TXD ),
      .ENET0_GMII_COL ( ENET0_GMII_COL ),
      .ENET0_GMII_CRS ( ENET0_GMII_CRS ),
      .ENET0_EXT_INTIN ( ENET0_EXT_INTIN ),
      .ENET0_GMII_RX_CLK ( ENET0_GMII_RX_CLK ),
      .ENET0_GMII_RX_DV ( ENET0_GMII_RX_DV ),
      .ENET0_GMII_RX_ER ( ENET0_GMII_RX_ER ),
      .ENET0_GMII_TX_CLK ( ENET0_GMII_TX_CLK ),
      .ENET0_MDIO_I ( ENET0_MDIO_I ),
      .ENET0_GMII_RXD ( ENET0_GMII_RXD ),
      .ENET1_GMII_TX_EN ( ENET1_GMII_TX_EN ),
      .ENET1_GMII_TX_ER ( ENET1_GMII_TX_ER ),
      .ENET1_MDIO_MDC ( ENET1_MDIO_MDC ),
      .ENET1_MDIO_O ( ENET1_MDIO_O ),
      .ENET1_MDIO_T ( ENET1_MDIO_T ),
      .ENET1_PTP_DELAY_REQ_RX ( ENET1_PTP_DELAY_REQ_RX ),
      .ENET1_PTP_DELAY_REQ_TX ( ENET1_PTP_DELAY_REQ_TX ),
      .ENET1_PTP_PDELAY_REQ_RX ( ENET1_PTP_PDELAY_REQ_RX ),
      .ENET1_PTP_PDELAY_REQ_TX ( ENET1_PTP_PDELAY_REQ_TX ),
      .ENET1_PTP_PDELAY_RESP_RX ( ENET1_PTP_PDELAY_RESP_RX ),
      .ENET1_PTP_PDELAY_RESP_TX ( ENET1_PTP_PDELAY_RESP_TX ),
      .ENET1_PTP_SYNC_FRAME_RX ( ENET1_PTP_SYNC_FRAME_RX ),
      .ENET1_PTP_SYNC_FRAME_TX ( ENET1_PTP_SYNC_FRAME_TX ),
      .ENET1_SOF_RX ( ENET1_SOF_RX ),
      .ENET1_SOF_TX ( ENET1_SOF_TX ),
      .ENET1_GMII_TXD ( ENET1_GMII_TXD ),
      .ENET1_GMII_COL ( ENET1_GMII_COL ),
      .ENET1_GMII_CRS ( ENET1_GMII_CRS ),
      .ENET1_EXT_INTIN ( ENET1_EXT_INTIN ),
      .ENET1_GMII_RX_CLK ( ENET1_GMII_RX_CLK ),
      .ENET1_GMII_RX_DV ( ENET1_GMII_RX_DV ),
      .ENET1_GMII_RX_ER ( ENET1_GMII_RX_ER ),
      .ENET1_GMII_TX_CLK ( ENET1_GMII_TX_CLK ),
      .ENET1_MDIO_I ( ENET1_MDIO_I ),
      .ENET1_GMII_RXD ( ENET1_GMII_RXD ),
      .GPIO_I ( GPIO_I ),
      .GPIO_O ( GPIO_O ),
      .GPIO_T ( GPIO_T ),
      .I2C0_SDA_I ( I2C0_SDA_I ),
      .I2C0_SDA_O ( I2C0_SDA_O ),
      .I2C0_SDA_T ( I2C0_SDA_T ),
      .I2C0_SCL_I ( I2C0_SCL_I ),
      .I2C0_SCL_O ( I2C0_SCL_O ),
      .I2C0_SCL_T ( I2C0_SCL_T ),
      .I2C1_SDA_I ( I2C1_SDA_I ),
      .I2C1_SDA_O ( I2C1_SDA_O ),
      .I2C1_SDA_T ( I2C1_SDA_T ),
      .I2C1_SCL_I ( I2C1_SCL_I ),
      .I2C1_SCL_O ( I2C1_SCL_O ),
      .I2C1_SCL_T ( I2C1_SCL_T ),
      .PJTAG_TCK ( PJTAG_TCK ),
      .PJTAG_TMS ( PJTAG_TMS ),
      .PJTAG_TD_I ( PJTAG_TD_I ),
      .PJTAG_TD_T ( PJTAG_TD_T ),
      .PJTAG_TD_O ( PJTAG_TD_O ),
      .SDIO0_CLK ( SDIO0_CLK ),
      .SDIO0_CLK_FB ( SDIO0_CLK_FB ),
      .SDIO0_CMD_O ( SDIO0_CMD_O ),
      .SDIO0_CMD_I ( SDIO0_CMD_I ),
      .SDIO0_CMD_T ( SDIO0_CMD_T ),
      .SDIO0_DATA_I ( SDIO0_DATA_I ),
      .SDIO0_DATA_O ( SDIO0_DATA_O ),
      .SDIO0_DATA_T ( SDIO0_DATA_T ),
      .SDIO0_LED ( SDIO0_LED ),
      .SDIO0_CDN ( SDIO0_CDN ),
      .SDIO0_WP ( SDIO0_WP ),
      .SDIO0_BUSPOW ( SDIO0_BUSPOW ),
      .SDIO0_BUSVOLT ( SDIO0_BUSVOLT ),
      .SDIO1_CLK ( SDIO1_CLK ),
      .SDIO1_CLK_FB ( SDIO1_CLK_FB ),
      .SDIO1_CMD_O ( SDIO1_CMD_O ),
      .SDIO1_CMD_I ( SDIO1_CMD_I ),
      .SDIO1_CMD_T ( SDIO1_CMD_T ),
      .SDIO1_DATA_I ( SDIO1_DATA_I ),
      .SDIO1_DATA_O ( SDIO1_DATA_O ),
      .SDIO1_DATA_T ( SDIO1_DATA_T ),