📄 system_processing_system7_0_wrapper.v
字号:
//-----------------------------------------------------------------------------
// system_processing_system7_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "processing_system7_v4_01_a" *)
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7,{C_I2C0_PERIPHERAL_ENABLE = 1,C_UART1_PERIPHERAL_ENABLE = 1,C_I2C0_I2C0_IO = MIO 50 .. 51,C_CAN0_CAN0_IO = MIO 46 .. 47,C_CAN0_PERIPHERAL_ENABLE = 1,C_SD0_GRP_CD_IO = MIO 0,C_SD0_GRP_CD_ENABLE = 1,C_TTC0_PERIPHERAL_ENABLE = 1,C_SD0_GRP_WP_IO = MIO 15,C_SD0_GRP_WP_ENABLE = 1,C_SD0_PERIPHERAL_ENABLE = 1,C_ENET0_GRP_MDIO_IO = MIO 52 .. 53,C_ENET0_PERIPHERAL_ENABLE = 1,C_ENET0_ENET0_IO = MIO 16 .. 27,C_ENET0_GRP_MDIO_ENABLE = 1,C_QSPI_PERIPHERAL_ENABLE = 1,C_QSPI_GRP_FBCLK_ENABLE = 1,C_USB0_PERIPHERAL_ENABLE = 1,C_WDT_PERIPHERAL_ENABLE = 1,C_PJTAG_PERIPHERAL_ENABLE = 0,C_MIO_MIO[12]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[10]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[8]_PULLUP = disabled,C_MIO_MIO[8]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[6]_PULLUP = disabled,C_MIO_MIO[6]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[5]_SLEW = fast,C_MIO_MIO[4]_PULLUP = disabled,C_MIO_MIO[4]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[3]_SLEW = fast,C_MIO_MIO[2]_PULLUP = disabled,C_MIO_MIO[2]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[1]_SLEW = fast,C_MIO_MIO[0]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[14]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[13]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[11]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[9]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[7]_PULLUP = disabled,C_MIO_MIO[7]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[6]_SLEW = fast,C_MIO_MIO[5]_PULLUP = disabled,C_MIO_MIO[5]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[4]_SLEW = fast,C_MIO_MIO[3]_PULLUP = disabled,C_MIO_MIO[3]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[2]_SLEW = fast,C_MIO_MIO[1]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[0]_SLEW = fast,C_MIO_MIO[31]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[30]_SLEW = fast,C_MIO_MIO[29]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[28]_SLEW = fast,C_MIO_MIO[27]_IOTYPE = HSTL 1.8V,C_MIO_MIO[26]_SLEW = fast,C_MIO_MIO[25]_IOTYPE = HSTL 1.8V,C_MIO_MIO[24]_SLEW = fast,C_MIO_MIO[23]_IOTYPE = HSTL 1.8V,C_MIO_MIO[22]_SLEW = fast,C_MIO_MIO[21]_IOTYPE = HSTL 1.8V,C_MIO_MIO[20]_SLEW = fast,C_MIO_MIO[19]_IOTYPE = HSTL 1.8V,C_MIO_MIO[18]_SLEW = fast,C_MIO_MIO[17]_IOTYPE = HSTL 1.8V,C_MIO_MIO[16]_SLEW = fast,C_MIO_MIO[15]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[31]_SLEW = fast,C_MIO_MIO[30]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[29]_SLEW = fast,C_MIO_MIO[28]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[27]_SLEW = fast,C_MIO_MIO[26]_IOTYPE = HSTL 1.8V,C_MIO_MIO[25]_SLEW = fast,C_MIO_MIO[24]_IOTYPE = HSTL 1.8V,C_MIO_MIO[23]_SLEW = fast,C_MIO_MIO[22]_IOTYPE = HSTL 1.8V,C_MIO_MIO[21]_SLEW = fast,C_MIO_MIO[20]_IOTYPE = HSTL 1.8V,C_MIO_MIO[19]_SLEW = fast,C_MIO_MIO[18]_IOTYPE = HSTL 1.8V,C_MIO_MIO[17]_SLEW = fast,C_MIO_MIO[16]_IOTYPE = HSTL 1.8V,C_MIO_MIO[15]_SLEW = fast,C_MIO_MIO[47]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[44]_SLEW = fast,C_MIO_MIO[43]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[42]_SLEW = fast,C_MIO_MIO[41]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[40]_SLEW = fast,C_MIO_MIO[39]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[38]_SLEW = fast,C_MIO_MIO[37]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[36]_SLEW = fast,C_MIO_MIO[35]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[34]_SLEW = fast,C_MIO_MIO[33]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[32]_SLEW = fast,C_MIO_MIO[46]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[45]_SLEW = fast,C_MIO_MIO[44]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[43]_SLEW = fast,C_MIO_MIO[42]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[41]_SLEW = fast,C_MIO_MIO[40]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[39]_SLEW = fast,C_MIO_MIO[38]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[37]_SLEW = fast,C_MIO_MIO[36]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[35]_SLEW = fast,C_MIO_MIO[34]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[33]_SLEW = fast,C_MIO_MIO[32]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[53]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[51]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[49]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[52]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[50]_IOTYPE = LVCMOS 1.8V,C_MIO_MIO[48]_IOTYPE = LVCMOS 1.8V,C_UIPARAM_DDR_PARTNO = MT41J256M8 HX-15E,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 = 0.089,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 = 0.217,C_UIPARAM_DDR_T_FAW = 30.0,C_UIPARAM_DDR_T_RC = 49.5,C_UIPARAM_DDR_T_RCD = 7,C_UIPARAM_DDR_CL = 7,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 = 0.248,C_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 = 0.133,C_UIPARAM_DDR_T_RAS_MIN = 36.0,C_UIPARAM_DDR_T_RP = 7,C_UIPARAM_DDR_CWL = 6,C_UIPARAM_DDR_FREQ_MHZ = 533.333313,C_UIPARAM_DDR_SPEED_BIN = DDR3_1066F,C_UIPARAM_DDR_DEVICE_CAPACITY = 2048 MBits,C_UIPARAM_DDR_DRAM_WIDTH = 8 Bits,C_UIPARAM_DDR_BL = 8,C_UIPARAM_DDR_MEMORY_TYPE = DDR 3,C_UIPARAM_DDR_BOARD_DELAY2 = 0.464,C_UIPARAM_DDR_BOARD_DELAY0 = 0.537,C_UIPARAM_DDR_USE_INTERNAL_VREF = 1,C_UIPARAM_DDR_TRAIN_READ_GATE = 1,C_UIPARAM_DDR_BOARD_DELAY3 = 0.521,C_UIPARAM_DDR_BOARD_DELAY1 = 0.442,C_UIPARAM_DDR_TRAIN_DATA_EYE = 1,C_UIPARAM_DDR_TRAIN_WRITE_LEVEL = 1,C_GPIO_PERIPHERAL_ENABLE = 1,C_CAN_PERIPHERAL_FREQMHZ = 23.8095,C_UART_PERIPHERAL_FREQMHZ = 50,C_PRESET_GLOBAL_DEFAULT = powerup,C_SDIO_PERIPHERAL_FREQMHZ = 50,C_ENET0_PERIPHERAL_FREQMHZ = 100 Mbps,C_APU_PERIPHERAL_FREQMHZ = 666.666666,C_PRESET_GLOBAL_CONFIG = Default,C_PRESET_BANK1_VOLTAGE = LVCMOS 1.8V,C_PSCONFIG_LVL_SHFTR_EN_C_USE_CR_FABRIC = 1,C_PRESET_BANK0_VOLTAGE = LVCMOS 1.8V}" *)
module system_processing_system7_0_wrapper
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
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