📄 system.vhd
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S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
-- Internal signals
signal axi_LDs_GPIO_IO_O : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_ARESETN : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(0 to 0);
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_lds_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
LD <= axi_LDs_GPIO_IO_O;
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => net_gnd0,
I2C0_SDA_O => open,
I2C0_SDA_T => open,
I2C0_SCL_I => net_gnd0,
I2C0_SCL_O => open,
I2C0_SCL_T => open,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
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