system_axi_lds_wrapper_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

    -----------------------------------------------------------------------
    Found 4-bit adder for signal <INCLUDE_DPHASE_TIMER.dpto_cnt[3]_GND_15_o_add_31_OUT> created at line 502.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <slave_attachment> synthesized.

Synthesizing Unit <address_decoder>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd".
        C_BUS_AWIDTH = 9
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000000000000000000000000000000000000","0000000000000000000000000000000000000000000000000000000000001111")
        C_ARD_NUM_CE_ARRAY = (4)
        C_FAMILY = "nofamily"
WARNING:Xst:647 - Input <Address_In_Erly<0:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus_RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <Bus_RNW_reg>.
    Found 1-bit register for signal <ce_out_i<0>>.
    Found 1-bit register for signal <ce_out_i<1>>.
    Found 1-bit register for signal <ce_out_i<2>>.
    Found 1-bit register for signal <ce_out_i<3>>.
    Found 1-bit register for signal <cs_out_i>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <address_decoder> synthesized.

Synthesizing Unit <pselect_f_1>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
        C_AB = 2
        C_AW = 2
        C_BAR = "00"
        C_FAMILY = "nofamily"
    Summary:
	inferred   1 Multiplexer(s).
Unit <pselect_f_1> synthesized.

Synthesizing Unit <pselect_f_2>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
        C_AB = 2
        C_AW = 2
        C_BAR = "01"
        C_FAMILY = "nofamily"
    Summary:
	inferred   1 Multiplexer(s).
Unit <pselect_f_2> synthesized.

Synthesizing Unit <pselect_f_3>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
        C_AB = 2
        C_AW = 2
        C_BAR = "10"
        C_FAMILY = "nofamily"
    Summary:
	inferred   1 Multiplexer(s).
Unit <pselect_f_3> synthesized.

Synthesizing Unit <pselect_f_4>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
        C_AB = 2
        C_AW = 2
        C_BAR = "11"
        C_FAMILY = "nofamily"
    Summary:
	inferred   1 Multiplexer(s).
Unit <pselect_f_4> synthesized.

Synthesizing Unit <GPIO_Core>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/gpio_core.vhd".
        C_DW = 32
        C_AW = 9
        C_GPIO_WIDTH = 8
        C_GPIO2_WIDTH = 32
        C_MAX_GPIO_WIDTH = 8
        C_INTERRUPT_PRESENT = 0
        C_DOUT_DEFAULT = "00000000000000000000000000000000"
        C_TRI_DEFAULT = "11111111111111111111111111111111"
        C_IS_DUAL = 0
        C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
        C_TRI_DEFAULT_2 = "11111111111111111111111111111111"
        C_FAMILY = "zynq"
WARNING:Xst:647 - Input <ABus_Reg<0:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ABus_Reg<7:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BE_Reg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <GPIO2_IO_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <gpio_xferAck_Reg>.
    Found 1-bit register for signal <GPIO_DBus_i<24>>.
    Found 1-bit register for signal <GPIO_DBus_i<25>>.
    Found 1-bit register for signal <GPIO_DBus_i<26>>.
    Found 1-bit register for signal <GPIO_DBus_i<27>>.
    Found 1-bit register for signal <GPIO_DBus_i<28>>.
    Found 1-bit register for signal <GPIO_DBus_i<29>>.
    Found 1-bit register for signal <GPIO_DBus_i<30>>.
    Found 1-bit register for signal <GPIO_DBus_i<31>>.
    Found 8-bit register for signal <gpio_io_i_d1>.
    Found 8-bit register for signal <gpio_io_i_d2>.
    Found 8-bit register for signal <gpio_Data_In>.
    Found 8-bit register for signal <gpio_Data_Out>.
    Found 8-bit register for signal <gpio_OE>.
    Found 1-bit register for signal <iGPIO_xferAck>.
    Summary:
	inferred  50 D-type flip-flop(s).
	inferred  19 Multiplexer(s).
Unit <GPIO_Core> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 4-bit adder                                           : 1
# Registers                                            : 32
 1-bit register                                        : 22
 2-bit register                                        : 2
 32-bit register                                       : 2
 4-bit register                                        : 1
 8-bit register                                        : 5
# Multiplexers                                         : 26
 1-bit 2-to-1 multiplexer                              : 24
 32-bit 2-to-1 multiplexer                             : 1
 9-bit 2-to-1 multiplexer                              : 1
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <slave_attachment>.
The following registers are absorbed into counter <INCLUDE_DPHASE_TIMER.dpto_cnt>: 1 register on signal <INCLUDE_DPHASE_TIMER.dpto_cnt>.
Unit <slave_attachment> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 130
 Flip-Flops                                            : 130
# Multiplexers                                         : 22
 1-bit 2-to-1 multiplexer                              : 20
 32-bit 2-to-1 multiplexer                             : 1
 9-bit 2-to-1 multiplexer                              : 1
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <s_axi_bresp_i_0> has a constant value of 0 in block <slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_axi_rresp_i_0> has a constant value of 0 in block <slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <s_axi_bresp_i_1> has a constant value of 0 in block <slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_axi_rresp_i_1> has a constant value of 0 in block <slave_attachment>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <axi_LDs/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/FSM_0> on signal <state[1:2]> with user encoding.
----------------------
 State    | Encoding
----------------------
 sm_idle  | 00
 sm_read  | 01
 sm_write | 10
 sm_resp  | 11
----------------------

Optimizing unit <system_axi_lds_wrapper> ...

Optimizing unit <axi_gpio> ...

Optimizing unit <slave_attachment> ...

Optimizing unit <address_decoder> ...

Optimizing unit <GPIO_Core> ...
WARNING:Xst:1710 - FF/Latch <axi_LDs/ip2bus_data_i_D1_23> (without init value) has a constant value of 0 in block <system_axi_lds_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <axi_LDs/ip2bus_data_i_D1_22> (without init value) has a constant value of 0 in block <system_axi_lds_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <axi_LDs/ip2bus_data_i_D1_21> (without init value) has a constant value of 0 in block <system_axi_lds_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <axi_LDs/ip2bus_data_i_D1_20> (without init value) has a constant value of 0 in block <system_axi_lds_wrapper>. This FF/Latch will be trimmed during the