system_axi_lds_wrapper_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Parsing entity <srl_fifo_rbu>.
Parsing architecture <imp> of entity <srl_fifo_rbu>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/valid_be.vhd" into library proc_common_v3_00_a
Parsing entity <valid_be>.
Parsing architecture <implementation> of entity <valid_be>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_with_enable_f.vhd" into library proc_common_v3_00_a
Parsing entity <or_with_enable_f>.
Parsing architecture <implementation> of entity <or_with_enable_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/muxf_struct_f.vhd" into library proc_common_v3_00_a
Parsing entity <muxf_struct>.
Parsing architecture <imp> of entity <muxf_struct>.
Parsing entity <muxf_struct_f>.
Parsing architecture <imp> of entity <muxf_struct_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/cntr_incr_decr_addn_f.vhd" into library proc_common_v3_00_a
Parsing entity <cntr_incr_decr_addn_f>.
Parsing architecture <imp> of entity <cntr_incr_decr_addn_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" into library proc_common_v3_00_a
Parsing entity <dynshreg_f>.
Parsing architecture <behavioral> of entity <dynshreg_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_i_f.vhd" into library proc_common_v3_00_a
Parsing entity <dynshreg_i_f>.
Parsing architecture <behavioral> of entity <dynshreg_i_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot_f.vhd" into library proc_common_v3_00_a
Parsing entity <mux_onehot_f>.
Parsing architecture <imp> of entity <mux_onehot_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu_f.vhd" into library proc_common_v3_00_a
Parsing entity <srl_fifo_rbu_f>.
Parsing architecture <imp> of entity <srl_fifo_rbu_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_f.vhd" into library proc_common_v3_00_a
Parsing entity <srl_fifo_f>.
Parsing architecture <imp> of entity <srl_fifo_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/compare_vectors_f.vhd" into library proc_common_v3_00_a
Parsing entity <compare_vectors_f>.
Parsing architecture <imp> of entity <compare_vectors_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" into library proc_common_v3_00_a
Parsing entity <pselect_f>.
Parsing architecture <imp> of entity <pselect_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" into library proc_common_v3_00_a
Parsing entity <counter_f>.
Parsing architecture <imp> of entity <counter_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy_f.vhd" into library proc_common_v3_00_a
Parsing entity <or_muxcy_f>.
Parsing architecture <implementation> of entity <or_muxcy_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate_f.vhd" into library proc_common_v3_00_a
Parsing entity <or_gate_f>.
Parsing architecture <imp> of entity <or_gate_f>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd" into library proc_common_v3_00_a
Parsing entity <soft_reset>.
Parsing architecture <implementation> of entity <soft_reset>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" into library interrupt_control_v2_01_a
Parsing entity <interrupt_control>.
Parsing architecture <implementation> of entity <interrupt_control>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/gpio_core.vhd" into library axi_gpio_v1_01_b
Parsing entity <GPIO_Core>.
Parsing architecture <IMP> of entity <gpio_core>.
Parsing VHDL file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd" into library axi_gpio_v1_01_b
Parsing entity <axi_gpio>.
Parsing architecture <imp> of entity <axi_gpio>.
Parsing VHDL file "D:\_prj\Xilinx\Blog\Lab3\hdl\system_axi_lds_wrapper.vhd" into library work
Parsing entity <system_axi_lds_wrapper>.
Parsing architecture <STRUCTURE> of entity <system_axi_lds_wrapper>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <system_axi_lds_wrapper> (architecture <STRUCTURE>) from library <work>.

Elaborating entity <axi_gpio> (architecture <imp>) with generics from library <axi_gpio_v1_01_b>.

Elaborating entity <axi_lite_ipif> (architecture <imp>) with generics from library <axi_lite_ipif_v1_01_a>.

Elaborating entity <slave_attachment> (architecture <imp>) with generics from library <axi_lite_ipif_v1_01_a>.
WARNING:HDLCompiler:746 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" Line 255: Range is empty (null range)

Elaborating entity <address_decoder> (architecture <IMP>) with generics from library <axi_lite_ipif_v1_01_a>.

Elaborating entity <pselect_f> (architecture <imp>) with generics from library <proc_common_v3_00_a>.

Elaborating entity <pselect_f> (architecture <imp>) with generics from library <proc_common_v3_00_a>.

Elaborating entity <pselect_f> (architecture <imp>) with generics from library <proc_common_v3_00_a>.

Elaborating entity <pselect_f> (architecture <imp>) with generics from library <proc_common_v3_00_a>.
INFO:HDLCompiler:679 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" Line 412. Case statement is complete. others clause is never selected

Elaborating entity <GPIO_Core> (architecture <IMP>) with generics from library <axi_gpio_v1_01_b>.
INFO:HDLCompiler:679 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/gpio_core.vhd" Line 335. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd" Line 504: Net <Bus2IP1_Data_i[8]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system_axi_lds_wrapper>.
    Related source file is "D:\_prj\Xilinx\Blog\Lab3\hdl\system_axi_lds_wrapper.vhd".
    Summary:
	no macro.
Unit <system_axi_lds_wrapper> synthesized.

Synthesizing Unit <axi_gpio>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd".
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
        C_FAMILY = "zynq"
        C_INSTANCE = "axi_LDs"
        C_S_AXI_ADDR_WIDTH = 9
        C_S_AXI_DATA_WIDTH = 32
        C_GPIO_WIDTH = 8
        C_GPIO2_WIDTH = 32
        C_ALL_INPUTS = 0
        C_ALL_INPUTS_2 = 0
        C_INTERRUPT_PRESENT = 0
        C_DOUT_DEFAULT = "00000000000000000000000000000000"
        C_TRI_DEFAULT = "11111111111111111111111111111111"
        C_IS_DUAL = 0
        C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
        C_TRI_DEFAULT_2 = "11111111111111111111111111111111"
WARNING:Xst:37 - Detected unknown constraint/property "IP_GROUP". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <S_AXI_ACLK>.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <S_AXI_ARESETN>.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "sigis". This constraint/property is not supported by the current software release and will be ignored.
INFO:Xst:3210 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd" line 554: Output port <Bus2IP_RdCE> of the instance <AXI_LITE_IPIF_I> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd" line 554: Output port <Bus2IP_WrCE> of the instance <AXI_LITE_IPIF_I> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd" line 783: Output port <GPIO_intr> of the instance <gpio_core_1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/hdl/vhdl/axi_gpio.vhd" line 783: Output port <GPIO2_intr> of the instance <gpio_core_1> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <Bus2IP1_Data_i<8:31>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ip2bus_rdack_i_D1>.
    Found 32-bit register for signal <ip2bus_data_i_D1>.
    Found 1-bit register for signal <bus2ip_reset>.
    Found 1-bit register for signal <ip2bus_wrack_i_D1>.
    Summary:
	inferred  35 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <axi_gpio> synthesized.

Synthesizing Unit <axi_lite_ipif>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd".
        C_S_AXI_DATA_WIDTH = 32
        C_S_AXI_ADDR_WIDTH = 9
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_USE_WSTRB = 0
        C_DPHASE_TIMEOUT = 8
        C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000000000000000000000000000000000000","0000000000000000000000000000000000000000000000000000000000001111")
        C_ARD_NUM_CE_ARRAY = (4)
        C_FAMILY = "zynq"
    Summary:
	no macro.
Unit <axi_lite_ipif> synthesized.

Synthesizing Unit <slave_attachment>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd".
        C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000000000000000000000000000000000000","0000000000000000000000000000000000000000000000000000000000001111")
        C_ARD_NUM_CE_ARRAY = (4)
        C_IPIF_ABUS_WIDTH = 9
        C_IPIF_DBUS_WIDTH = 32
        C_S_AXI_MIN_SIZE = "00000000000000000000000111111111"
        C_USE_WSTRB = 0
        C_DPHASE_TIMEOUT = 8
        C_FAMILY = "zynq"
WARNING:Xst:647 - Input <S_AXI_WSTRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" line 336: Output port <CS_for_gaps> of the instance <I_DECODER> is unconnected or connected to loadless signal.
    Found 2-bit register for signal <state>.
    Found 2-bit register for signal <s_axi_rresp_i>.
    Found 32-bit register for signal <s_axi_rdata_i>.
    Found 1-bit register for signal <s_axi_rvalid_i>.
    Found 2-bit register for signal <s_axi_bresp_i>.
    Found 1-bit register for signal <s_axi_bvalid_i>.
    Found 4-bit register for signal <INCLUDE_DPHASE_TIMER.dpto_cnt>.
    Found 1-bit register for signal <rst>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 6                                              |
    | Outputs            | 4                                              |
    | Clock              | S_AXI_ACLK (rising_edge)                       |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | sm_idle                                        |
    | Power Up State     | sm_idle                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |