system_axi_interconnect_1_wrapper_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_carry_latch_or.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_carry_latch_or>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_carry_or.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_carry_or>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_carry.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_carry>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_command_fifo.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_command_fifo>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_mask_static.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_mask_static>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_mask.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_mask>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_sel_mask_static.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_sel_mask_static>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_sel_mask.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_sel_mask>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_sel_static.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_sel_static>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_sel.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_sel>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator_static.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator_static>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_comparator.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_comparator>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_converter_bank.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_converter_bank>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_crossbar_sasd.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_crossbar_sasd>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_crossbar.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_crossbar>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_data_fifo_bank.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_data_fifo_bank>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_decerr_slave.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_decerr_slave>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_fifo_gen.v" into library axi_interconnect_v1_06_a
Parsing module <fifo_generator_v9_1>.
Parsing module <ict106_fifo_gen>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_mux_enc.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_mux_enc>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_mux.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_mux>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_ndeep_srl.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_ndeep_srl>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_nto1_mux.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_nto1_mux>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_protocol_conv_bank.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_protocol_conv_bank>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_r_axi3_conv.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_r_axi3_conv>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_r_downsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_r_downsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_register_slice_bank.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_register_slice_bank>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_r_upsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_r_upsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_si_transactor.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_si_transactor>.