system_axi_interconnect_1_wrapper_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

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Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_sample_cycle_ratio.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axic_sample_cycle_ratio>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_sync_clock_converter.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axic_sync_clock_converter>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_a_axi3_conv.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_a_axi3_conv>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_addr_arbiter_sasd.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_addr_arbiter_sasd>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_addr_arbiter.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_addr_arbiter>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_addr_decoder.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_addr_decoder>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_a_downsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_a_downsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_arbiter_resp.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_arbiter_resp>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_a_upsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_a_upsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi3_conv.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi3_conv>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_fifo.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axic_fifo>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_clock_converter.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_clock_converter>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_register_slice.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axic_register_slice>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_reg_srl_fifo.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axic_reg_srl_fifo>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_crossbar.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_crossbar>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_srl_fifo.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axic_srl_fifo>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_data_fifo.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_data_fifo>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_downsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_downsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axilite_conv.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axilite_conv>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_protocol_converter.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_protocol_converter>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_register_slice.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_register_slice>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_axi_upsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_axi_upsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_b_downsizer.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_b_downsizer>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_carry_and.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_carry_and>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog/ict106_carry_latch_and.v" into library axi_interconnect_v1_06_a
Parsing module <ict106_carry_latch_and>.