system_axi_interconnect_1_wrapper_xst.scr

来自「自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）」· SCR 代码 · 共 15 行

set -tmpdir D:\_prj\Xilinx\Blog\Lab3\synthesis\xst_temp_dir\
run
-opt_mode speed
-netlist_hierarchy as_optimized
-opt_level 1
-p xc7z020clg484-1
-top system_axi_interconnect_1_wrapper
-ifmt MIXED
-ifn system_axi_interconnect_1_wrapper_xst.prj
-ofn ../implementation/system_axi_interconnect_1_wrapper.ngc
-hierarchy_separator /
-iobuf NO
-sd {../implementation}
-vlgincdir {"D:\_prj\Xilinx\Blog\Lab3\pcores\" "C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxBFMinterface\pcores\" "C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }