system_processing_system7_0_wrapper_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

WARNING:Xst:653 - Signal <FTMD_TRACEIN_DATA_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <FTMD_TRACEIN_ATID_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET0_GMII_COL_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET0_GMII_CRS_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET0_GMII_RX_DV_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET0_GMII_RX_ER_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET1_GMII_COL_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET1_GMII_CRS_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET1_GMII_RX_DV_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET1_GMII_RX_ER_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <FTMD_TRACEIN_VALID_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <processing_system7> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

WARNING:Xst:528 - Multi-source in Unit <processing_system7> on signal <PS_SRSTB>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <PS_SRSTB>
   Output port PS7:PSSRSTB of instance <processing_system7_0/PS7_i>

WARNING:Xst:528 - Multi-source in Unit <processing_system7> on signal <PS_CLK>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <PS_CLK>
   Output port PS7:PSCLK of instance <processing_system7_0/PS7_i>

WARNING:Xst:528 - Multi-source in Unit <processing_system7> on signal <PS_PORB>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <PS_PORB>
   Output port PS7:PSPORB of instance <processing_system7_0/PS7_i>

Optimizing unit <system_processing_system7_0_wrapper> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block system_processing_system7_0_wrapper, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : system_processing_system7_0_wrapper.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 90
#      GND                         : 1
#      INV                         : 89
# Clock Buffers                    : 1
#      BUFG                        : 1
# Others                           : 1
#      PS7                         : 1

Device utilization summary:
---------------------------

Selected Device : 7z020clg484-1 


Slice Logic Utilization: 
 Number of Slice LUTs:                   89  out of  53200     0%  
    Number used as Logic:                89  out of  53200     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     89
   Number with an unused Flip Flop:      89  out of     89   100%  
   Number with an unused LUT:             0  out of     89     0%  
   Number of fully used LUT-FF pairs:     0  out of     89     0%  
   Number of unique control sets:         0

IO Utilization: 
 Number of IOs:                        3308
 Number of bonded IOBs:                   0  out of    200     0%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.466ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 3201 / 3201
-------------------------------------------------------------------------
Delay:               0.466ns (Levels of Logic = 1)
  Source:            processing_system7_0/PS7_i:EMIOGPIOTN63 (PAD)
  Destination:       GPIO_T<63> (PAD)

  Data Path: processing_system7_0/PS7_i:EMIOGPIOTN63 to GPIO_T<63>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    PS7:EMIOGPIOTN63       1   0.000   0.399  processing_system7_0/PS7_i (processing_system7_0/gpio_out_t_n<63>)
     INV:I->O              0   0.067   0.000  processing_system7_0/GPIO_T<63>1_INV_0 (GPIO_T<63>)
    ----------------------------------------
    Total                      0.466ns (0.067ns logic, 0.399ns route)
                                       (14.4% logic, 85.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

=========================================================================


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.84 secs
 
--> 

Total memory usage is 243672 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   68 (   0 filtered)
Number of infos    :    0 (   0 filtered)