system_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Release 14.2 - xst P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to D:\_prj\Xilinx\Blog\Lab3\synthesis\xst_temp_dir\


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
 
--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"
Verilog Include Directory          : {"D:\_prj\Xilinx\Blog\Lab3\pcores\" "C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxBFMinterface\pcores\" "C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc7z020clg484-1
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 10000

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "D:\_prj\Xilinx\Blog\Lab3\hdl\system.vhd" into library work
Parsing entity <system>.
Parsing architecture <STRUCTURE> of entity <system>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <system> (architecture <STRUCTURE>) from library <work>.
WARNING:HDLCompiler:634 - "D:\_prj\Xilinx\Blog\Lab3\hdl\system.vhd" Line 983: Net <axi_interconnect_1_S_ARLEN[7]> does not have a driver.
WARNING:HDLCompiler:634 - "D:\_prj\Xilinx\Blog\Lab3\hdl\system.vhd" Line 994: Net <axi_interconnect_1_S_AWLEN[7]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system>.
    Related source file is "D:\_prj\Xilinx\Blog\Lab3\hdl\system.vhd".
    Set property "BOX_TYPE = user_black_box" for instance <processing_system7_0>.
    Set property "BOX_TYPE = user_black_box" for instance <axi_LDs>.