📄 platform.c
字号:
/* * Copyright (c) 2010 Xilinx, Inc. All rights reserved. * * Xilinx, Inc. * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. * */#include "xparameters.h"#include "xil_cache.h"#include "platform_config.h"#ifdef STDOUT_IS_16550#include "xuartns550_l.h"#endifvoidenable_caches(){#ifdef __PPC__ Xil_ICacheEnableRegion(XPAR_CACHEABLE_REGION_MASK); // Do not enable caches for memory tests, this has pros and cons // Pros - If caches are enabled, under certain configurations, there will be very few // transactions to external memory // Con - This might not generate a burst cacheline request // Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);#elif __MICROBLAZE__#ifdef XPAR_MICROBLAZE_USE_ICACHE Xil_ICacheEnable();#endif#ifdef XPAR_MICROBLAZE_USE_DCACHE // See reason above for not enable D Cache // Xil_DCacheEnable();#endif#endif}voiddisable_caches(){ Xil_DCacheDisable(); Xil_ICacheDisable();}voidinit_platform(){ enable_caches(); /* if we have a uart 16550, then that needs to be initialized */#ifdef STDOUT_IS_16550 XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600); XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);#endif}voidcleanup_platform(){ disable_caches();}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -