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📄 xdevcfg.c

📁 自学ZedBoard:使用IP通过ARM PS访问FPGA(源代码)
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/******************************************************************************** (c) Copyright 2011-12 Xilinx, Inc. All rights reserved.** This file contains confidential and proprietary information of Xilinx, Inc.* and is protected under U.S. and international copyright and other* intellectual property laws.** DISCLAIMER* This disclaimer is not a license and does not grant any rights to the* materials distributed herewith. Except as otherwise provided in a valid* license issued to you by Xilinx, and to the maximum extent permitted by* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;* and (2) Xilinx shall not be liable (whether in contract or tort, including* negligence, or under any other theory of liability) for any loss or damage* of any kind or nature related to, arising under or in connection with these* materials, including for any direct, or any indirect, special, incidental,* or consequential loss or damage (including loss of data, profits, goodwill,* or any type of loss or damage suffered as a result of any action brought by* a third party) even if such damage or loss was reasonably foreseeable or* Xilinx had been advised of the possibility of the same.** CRITICAL APPLICATIONS* Xilinx products are not designed or intended to be fail-safe, or for use in* any application requiring fail-safe performance, such as life-support or* safety devices or systems, Class III medical devices, nuclear facilities,* applications related to the deployment of airbags, or any other applications* that could lead to death, personal injury, or severe property or* environmental damage (individually and collectively, "Critical* Applications"). Customer assumes the sole risk and liability of any use of* Xilinx products in Critical Applications, subject only to applicable laws* and regulations governing limitations on product liability.** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE* AT ALL TIMES.*******************************************************************************//****************************************************************************//**** @file xdevcfg.c** This file contains the implementation of the interface functions for XDcfg* driver. Refer to the header file xdevcfg.h for more detailed information.** <pre>* MODIFICATION HISTORY:** Ver   Who Date     Changes* ----- --- -------- ---------------------------------------------* 1.00a hvm 02/07/11 First release* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer*		     APIs is words (32 bit) and not bytes.* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs*		     to add information that 2 LSBs of the Source/Destination*		     address when equal to 2抌01 indicate the last DMA command*		     of an overall transfer.*		     Updated the XDcfg_Transfer function to use the*		     Destination Address passed to this API for secure transfers*		     instead of using 0xFFFFFFFF for CR 662197. This issue was*		     resulting in the failure of secure transfers of*		     non-bitstream images.* </pre>*******************************************************************************//***************************** Include Files *********************************/#include "xdevcfg.h"/************************** Constant Definitions *****************************//**************************** Type Definitions *******************************//***************** Macros (Inline Functions) Definitions *********************//************************** Function Prototypes ******************************//************************** Variable Definitions *****************************//****************************************************************************//**** Initialize the Device Config Interface driver. This function* must be called before other functions of the driver are called.** @param	InstancePtr is a pointer to the XDcfg instance.* @param	ConfigPtr is the config structure.* @param	EffectiveAddress is the base address for the device. It could be*		a virtual address if address translation is supported in the*		system, otherwise it is the physical address.** @return*		- XST_SUCCESS if initialization was successful.*		- XST_DEVICE_IS_STARTED if the device has already been started.** @note		The very first APB access to the Device Configuration Interface*		block needs to be a write to the UNLOCK register with the value*		of 0x757BDF0D. This step is to be done once after reset, any*		other APB access has to come after this. The APB access is*		considered illegal if the step is not done or if it is done*		incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,*		the following additional actions would be carried out.*		In other words, if all bits are low, the following steps are not*		done.*			1. AES is disabled*			2. All APB writes disabled*			3. SoC debug fully enabled*******************************************************************************/int XDcfg_CfgInitialize(XDcfg *InstancePtr,			 XDcfg_Config *ConfigPtr, u32 EffectiveAddress){	Xil_AssertNonvoid(InstancePtr != NULL);	Xil_AssertNonvoid(ConfigPtr != NULL);	/*	 * If the device is started, disallow the initialize and return a	 * status indicating it is started. This allows the user to stop the	 * device and reinitialize, but prevents a user from inadvertently	 * initializing.	 */	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {		return XST_DEVICE_IS_STARTED;	}	/*	 * Copy configuration into instance.	 */	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;	/*	 * Save the base address pointer such that the registers of the block	 * can be accessed and indicate it has not been started yet.	 */	InstancePtr->Config.BaseAddr = EffectiveAddress;	InstancePtr->IsStarted = 0;	/* Unlock the Device Configuration Interface */	XDcfg_Unlock(InstancePtr);	/*	 * Indicate the instance is ready to use, successfully initialized.	 */	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;	return XST_SUCCESS;}/****************************************************************************//**** The functions enables the PCAP interface by setting the PCAP mode bit in the* control register.** @param	InstancePtr is a pointer to the XDcfg instance.** @return	None.** @note		Enable FPGA programming	from PCAP interface. Enabling this bit*		disables all the external interfaces from programming of FPGA*		except for ICAP. The user needs to ensure that the FPGA is*		programmed through either PCAP or ICAP.******************************************************************************/void XDcfg_EnablePCAP(XDcfg *InstancePtr){	u32 CtrlReg;	/*	 * Assert the arguments.	 */	Xil_AssertVoid(InstancePtr != NULL);	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,					XDCFG_CTRL_OFFSET);	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,			(CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));}/****************************************************************************//**** The functions disablees the PCAP interface by clearing the PCAP mode bit in* the control register.** @param	InstancePtr is a pointer to the XDcfg instance.** @return	None.** @note		None.******************************************************************************/void XDcfg_DisablePCAP(XDcfg *InstancePtr){	u32 CtrlReg;	/*	 * Assert the arguments.	 */	Xil_AssertVoid(InstancePtr != NULL);	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,					XDCFG_CTRL_OFFSET);	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,			(CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));}/****************************************************************************//**** The function sets the contents of the Control Register.** @param	InstancePtr is a pointer to the XDcfg instance.* @param	Mask is the 32 bit mask data to be written to the Register.*		The mask definitions are defined in the xdevcfg_hw.h file.** @return	None.** @note		None.******************************************************************************/void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask){	u32 CtrlReg;	/*	 * Assert the arguments.	 */	Xil_AssertVoid(InstancePtr != NULL);	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,					XDCFG_CTRL_OFFSET);	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,			(CtrlReg | Mask));}/****************************************************************************//**** The function reads the contents of the Control Register.** @param	InstancePtr is a pointer to the XDcfg instance.** @return	A 32-bit value representing the contents of the Control*		Register.*		Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to*		interpret the returned value.** @note		None.******************************************************************************/u32 XDcfg_GetControlRegister(XDcfg *InstancePtr){	/*	 * Assert the arguments.	 */	Xil_AssertNonvoid(InstancePtr != NULL);	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	/*	 * Read the Control Register and return the value.	 */	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);}/****************************************************************************//**** The function sets the contents of the Lock Register. These bits* can only be set to a 1. They will be cleared after a Power On Reset.** @param	InstancePtr is a pointer to the XDcfg instance.* @param	Data is the 32 bit data to be written to the Register.** @return	None.** @note		None.******************************************************************************/void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data){	/*	 * Assert the arguments.	 */	Xil_AssertVoid(InstancePtr != NULL);	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);}/****************************************************************************//**** The function reads the contents of the Lock Register.** @param	InstancePtr is a pointer to the XDcfg instance.** @return	A 32-bit value representing the contents of the Lock*		Register.*		Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to*		interpret the returned value.** @note		None.******************************************************************************/u32 XDcfg_GetLockRegister(XDcfg *InstancePtr){	/*	 * Assert the arguments.	 */	Xil_AssertNonvoid(InstancePtr != NULL);	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	/*	 * Read the Lock Register and return the value.	 */	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);}/****************************************************************************//**** The function sets the contents of the Configuration Register with the* given value.** @param	InstancePtr is a pointer to the XDcfg instance.* @param	Data is the 32 bit data to be written to the Register.** @return	None.** @note		None.******************************************************************************/void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data){	/*	 * Assert the arguments.	 */	Xil_AssertVoid(InstancePtr != NULL);	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);}/****************************************************************************//**** The function reads the contents of the Configuration Register with the* given value.** @param	InstancePtr is a pointer to the XDcfg instance.** @return	A 32-bit value representing the contents of the Config*		Register.*		Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to*		interpret the returned value.** @note		None.******************************************************************************/u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr){	/*	 * Assert the arguments.	 */	Xil_AssertNonvoid(InstancePtr != NULL);	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);}/****************************************************************************//**** The function sets the contents of the Status Register.** @param	InstancePtr is a pointer to the XDcfg instance.* @param	Data is the 32 bit data to be written to the Register.** @return	None.** @note		None.******************************************************************************/void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data){	/*	 * Assert the arguments.	 */	Xil_AssertVoid(InstancePtr != NULL);	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);}/****************************************************************************//**** The function reads the contents of the Status Register.** @param	InstancePtr is a pointer to the XDcfg instance.** @return	A 32-bit value representing the contents of the Status*		Register.*		Use the XDCFG_STATUS_*_MASK constants defined in*		xdevcfg_hw.h to interpret the returned value.** @note		None.******************************************************************************/u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr){	/*

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