xwdtps_hw.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

/* $Id: xwdtps_hw.h,v 1.1.2.1 2011/01/20 04:17:15 sadanan Exp $ */
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/**
*
* @file xwdtps_hw.h
*
* This file contains the hardware interface to the Watch Dog Timer (WDT).
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who    Date     Changes
* ----- ------ -------- ---------------------------------------------
* 1.00a ecm/jz 01/15/10 First release
* </pre>
*
******************************************************************************/
#ifndef XWDTPS_HW_H		/* prevent circular inclusions */
#define XWDTPS_HW_H		/* by using protection macros */

#ifdef __cplusplus
extern "C" {
#endif

/***************************** Include Files *********************************/

#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"

/************************** Constant Definitions *****************************/

/** @name Register Map
 * Offsets of registers from the start of the device
 * @{
 */

#define XWDTPS_ZMR_OFFSET	0x0 /**< Zero Mode Register */
#define XWDTPS_CCR_OFFSET	0x4 /**< Conunter Control Register */
#define XWDTPS_RESTART_OFFSET	0x8 /**< Restart Register */
#define XWDTPS_SR_OFFSET	0xC /**< Status Register */
/* @} */


/** @name Zero Mode Register
 * This register controls how the time out is indicated
 * and also contains the access code to allow
 * writes to the register (0xABC)
 * @{
 */
#define XWDTPS_ZMR_WDEN_MASK	0x00000001 /**< enable the WDT */
#define XWDTPS_ZMR_RSTEN_MASK	0x00000002 /**< enable the reset output */
#define XWDTPS_ZMR_IRQEN_MASK	0x00000004 /**< enable the IRQ output */
#define XWDTPS_ZMR_EXTEN_MASK	0x00000008 /**< enable the External output */

#define XWDTPS_ZMR_RSTLN_MASK	0x00000070 /**< set length of reset pulse */
#define XWDTPS_ZMR_RSTLN_SHIFT	4	   /**< shift for reset pulse */

#define XWDTPS_ZMR_IRQLN_MASK	0x00000180 /**< set length of interrupt pulse */
#define XWDTPS_ZMR_IRQLN_SHIFT	7	   /**< shift for interrupt pulse */

#define XWDTPS_ZMR_EXLN_MASK	0x00000E00 /**< set length of External pulse */
#define XWDTPS_ZMR_EXLN_SHIFT	9	   /**< shift for External pulse */

#define XWDTPS_ZMR_ZKEY_MASK	0x00FFF000 /**< mask for writing access key */
#define XWDTPS_ZMR_ZKEY_VAL	0x00ABC000 /**< access key, 0xABC << 12 */

/* Bit patterns for External signal pulse length */

#define XWDTPS_ZMR_EXLN_0008	0x00000000 /**< len of External-8 clocks */
#define XWDTPS_ZMR_EXLN_0016	0x00000001 /**< len of External-16 clocks */
#define XWDTPS_ZMR_EXLN_0032	0x00000002 /**< len of External-32 clocks */
#define XWDTPS_ZMR_EXLN_0064	0x00000003 /**< len of External-64 clocks */
#define XWDTPS_ZMR_EXLN_0128	0x00000004 /**< len of External-128 clocks */
					/**<  256 is not valid */
#define XWDTPS_ZMR_EXLN_0512	0x00000005 /**< len of External-512 clocks */
#define XWDTPS_ZMR_EXLN_1024	0x00000006 /**< len of External-1024 clocks */
#define XWDTPS_ZMR_EXLN_2048	0x00000007 /**< len of External-2048 clocks */
/* @} */

/** @name  Counter Control register
 * This register controls how fast the timer runs and the reset value
 * and also contains the access code to allow
 * writes to the register (0x448)
 * @{
 */

#define XWDTPS_CCR_CLKSEL_MASK	0x00000003 /**< counter clock prescale */

#define XWDTPS_CCR_CRV_MASK	0x00003FFC /**< counter reset value */
#define XWDTPS_CCR_CRV_SHIFT	2	   /**< shift for writing value */

#define XWDTPS_CCR_CKEY_MASK	0x03FFC000 /**< mask for writing access key */
#define XWDTPS_CCR_CKEY_VAL	0x00920000 /**< ccess key, 0x448 << 6 */

/* Bit patterns for Clock prescale divider values */

#define XWDTPS_CCR_PSCALE_0008   0x00000000 /**< divide clock by 8 */
#define XWDTPS_CCR_PSCALE_0064   0x00000001 /**< divide clock by 64 */
#define XWDTPS_CCR_PSCALE_0512   0x00000002 /**< divide clock by 512 */
#define XWDTPS_CCR_PSCALE_4096   0x00000003 /**< divide clock by 4096 */

/* @} */

/** @name  Restart register
 * This register resets the timer preventing a timeout. Value is specific
 * 0x1999
 * @{
 */

#define XWDTPS_RESTART_KEY_VAL	0x00001999 /**< valid key */

/*@}*/

/** @name Status register
 * This register indicates timer reached zero.
 * @{
 */
#define XWDTPS_SR_WDZ_MASK	0x00000001 /**< time out occured */

/*@}*/

/**************************** Type Definitions *******************************/


/***************** Macros (Inline Functions) Definitions *********************/

/****************************************************************************/
/**
*
* Read the given register.
*
* @param	BaseAddress is the base address of the device
* @param	RegOffset is the register offset to be read
*
* @return	The 32-bit value of the register
*
* @note		C-style signature:
*		u32 XWdtPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XWdtPs_ReadReg(BaseAddress, RegOffset) \
	Xil_In32((BaseAddress) + (RegOffset))

/****************************************************************************/
/**
*
* Write the given register.
*
* @param	BaseAddress is the base address of the device
* @param	RegOffset is the register offset to be written
* @param	Data is the 32-bit value to write to the register
*
* @return	None.
*
* @note		C-style signature:
*		void XWdtPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XWdtPs_WriteReg(BaseAddress, RegOffset, Data) \
	Xil_Out32((BaseAddress) + (RegOffset), (Data))


/************************** Function Prototypes ******************************/


/************************** Variable Definitions *****************************/

#ifdef __cplusplus
}
#endif

#endif