xadcps.c

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

	/*
	 * Read the channel sequencer mode from the Configuration Register 1.
	 */
	return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
			XADCPS_CFR1_SEQ_SHIFT));

}

/****************************************************************************/
/**
*
* The function sets the frequency of the ADCCLK by configuring the DCLK to
* ADCCLK ratio in the Configuration Register #2
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
*		Valid values of the divisor are
*		 - 0 to 255. Values 0, 1, 2 are all mapped to 2.
*		Refer to the device specification for more details
*
* @return	None.
*
* @note		- The ADCCLK is an internal clock used by the ADC and is
*		  synchronized to the DCLK clock. The ADCCLK is equal to DCLK
*		  divided by the user selection in the Configuration Register 2.
*		- There is no Assert on the minimum value of the Divisor.
*
*****************************************************************************/
void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Write the divisor value into the Configuration Register #2.
	 */
	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
			  Divisor << XADCPS_CFR2_CD_SHIFT);

}

/****************************************************************************/
/**
*
* The function gets the ADCCLK divisor from the Configuration Register 2.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
*
* @return	The divisor read from the Configuration Register 2.
*
* @note		The ADCCLK is an internal clock used by the ADC and is
*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
*		divided by the user selection in the Configuration Register 2.
*
*****************************************************************************/
u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
{
	u16 Divisor;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Read the divisor value from the Configuration Register 2.
	 */
	Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
					 XADCPS_CFR2_OFFSET);

	return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
}

/****************************************************************************/
/**
*
* This function enables the specified channels in the ADC Channel Selection
* Sequencer Registers. The sequencer must be disabled before writing to these
* regsiters.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
* @param	ChEnableMask is the bit mask of all the channels to be enabled.
*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
*		be disabled.
*		The ChEnableMask is a 32 bit mask that is written to the two
*		16 bit ADC Channel Selection Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Selection Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None
*
*****************************************************************************/
int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be disabled for writing any of these registers
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */
	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SINGCHAN)) {
		return XST_FAILURE;
	}

	/*
	 * Enable the specified channels in the ADC Channel Selection Sequencer
	 * Registers.
	 */
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ00_OFFSET,
				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));

	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ01_OFFSET,
				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ01_CH_VALID_MASK);

	return XST_SUCCESS;
}

/****************************************************************************/
/**
*
* This function gets the channel enable bits status from the ADC Channel
* Selection Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
*
* @return	Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
*		xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
*		are the channels that are enabled and bit mask of 0 are
*		the channels that are disabled.
*
* @return	None
*
* @note		None
*
*****************************************************************************/
u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
{
	u32 RegValEnable;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 *  Read the channel enable bits for all the channels from the ADC
	 *  Channel Selection Register.
	 */
	RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
				XADCPS_SEQ00_OFFSET) &
				XADCPS_SEQ00_CH_VALID_MASK;
	RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
				XADCPS_SEQ01_OFFSET) &
				XADCPS_SEQ01_CH_VALID_MASK) <<
				XADCPS_SEQ_CH_AUX_SHIFT;


	return RegValEnable;
}

/****************************************************************************/
/**
*
* This function enables the averaging for the specified channels in the ADC
* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
* before writing to these regsiters.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
* @param	AvgEnableChMask is the bit mask of all the channels for which
*		averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
*		xadcps_hw.h to specify the Channel numbers. Averaging will be
*		enabled for bit masks of 1 and disabled for bit mask of 0.
*		The AvgEnableChMask is a 32 bit mask that is written to the two
*		16 bit ADC Channel Averaging Enable Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Averaging Enables Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None
*
*****************************************************************************/
int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be disabled for writing any of these registers
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */
	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SINGCHAN)) {
		return XST_FAILURE;
	}

	/*
	 * Enable/disable the averaging for the specified channels in the
	 * ADC Channel Averaging Enables Sequencer Registers.
	 */
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ02_OFFSET,
				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));

	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ03_OFFSET,
				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ03_CH_VALID_MASK);

	return XST_SUCCESS;
}

/****************************************************************************/
/**
*
* This function returns the channels for which the averaging has been enabled
* in the ADC Channel Averaging Enables Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
*
* @returns 	The status of averaging (enabled/disabled) for all the channels.
*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
*		Channel numbers. Bit masks of 1 are the channels for which
*		averaging is enabled and bit mask of 0 are the channels for
*		averaging is disabled
*
* @note		None
*
*****************************************************************************/
u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
{
	u32 RegValAvg;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Read the averaging enable status for all the channels from the
	 * ADC Channel Averaging Enables Sequencer Registers.
	 */
	RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
				XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
	RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
			XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
			XADCPS_SEQ_CH_AUX_SHIFT;

	return RegValAvg;
}

/****************************************************************************/
/**
*
* This function sets the Analog input mode for the specified channels in the ADC
* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
* before writing to these regsiters.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
* @param	InputModeChMask is the bit mask of all the channels for which
*		the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
*		in xadcps_hw.h to specify the channel numbers. Differential
*		input mode will be set for bit masks of 1 and unipolar input
*		mode for bit masks of 0.
*		The InputModeChMask is a 32 bit mask that is written to the two
*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Analog-Input Mode Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None
*
*****************************************************************************/
int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be disabled for writing any of these registers
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */
	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SINGCHAN)) {
		return XST_FAILURE;
	}

	/*
	 * Set the input mode for the specified channels in the ADC Channel
	 * Analog-Input Mode Sequencer Registers.
	 */
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ04_OFFSET,
				(InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));

	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ05_OFFSET,
				(InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ05_CH_VALID_MASK);

	return XST_SUCCESS;
}

/****************************************************************************/
/**
*
* This function gets the Analog input mode for all the channels from
* the ADC Channel Analog-Input Mode Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
*
* @returns 	The input mode for all the channels.
*		Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
*		Channel numbers. Bit masks of 1 are the channels for which
*		input mode is differential and bit mask of 0 are the channels
*		for which input mode is unipolar.
*
* @note		None.
*
*****************************************************************************/
u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
{
	u32 InputMode;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 *  Get the input mode for all the channels from the ADC Channel
	 * Analog-Input Mode Sequencer Registers.
	 */
	InputMode = XAdcPs_ReadInternalReg(InstancePtr,
				XADCPS_SEQ04_OFFSET) &
				XADCPS_SEQ04_CH_VALID_MASK;
	InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
				XADCPS_SEQ05_OFFSET) &
				XADCPS_SEQ05_CH_VALID_MASK) <<
				XADCPS_SEQ_CH_AUX_SHIFT;

	return InputMode;
}

/****************************************************************************/
/**
*
* This function sets the number of Acquisition cycles in the ADC Channel
* Acquisition Time Sequencer Registers. The sequencer must be disabled
* before writing to these regsiters.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
* @param	AcqCyclesChMask is the bit mask of all the channels for which
*		the number of acquisition cycles is to be extended.
*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
*		bit masks of 0.
*		The AcqCyclesChMask is a 32 bit mask that is written to the two
*		16 bit ADC Channel Acquisition Time Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the Channel Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be disabled for writing any of these registers
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */
	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
			XADCPS_SEQ_MODE_SINGCHAN)) {
		return XST_FAILURE;
	}

	/*
	 * Set the Acquisition time for the specified channels in the
	 * ADC Channel Acquisition Time Sequencer Registers.
	 */
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ06_OFFSET,
				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));

	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ07_OFFSET,
				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ07_CH_VALID_MASK);

	return XST_SUCCESS;
}

/****************************************************************************/
/**
*
* This function gets the status of acquisition from the ADC Channel Acquisition
* Time Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XAdcPs instance.
*
* @returns 	The acquisition time for all the channels.
*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
*		Channel numbers. Bit masks of 1 are the channels for which
*		acquisition cycles are extended and bit mask of 0 are the
*		channels for which acquisition cycles are not extended.
*
* @note		None
*
*****************************************************************************/
u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
{
	u32 RegValAcq;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Get the Acquisition cycles for the specified channels from the ADC
	 * Channel Acquisition Time Sequencer Registers.