xusbps_hw.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

#define XUSBPS_IXR_SLE_MASK	0x00000100 /**< Device Controller Suspend */
#define XUSBPS_IXR_ULPI_MASK	0x00000400 /**< ULPI IRQ */
#define XUSBPS_IXR_HCH_MASK	0x00001000 /**< Host Controller Halted
						* Read Only */
#define XUSBPS_IXR_RCL_MASK	0x00002000 /**< USB Reclamation  Read Only */
#define XUSBPS_IXR_PS_MASK	0x00004000 /**< Periodic Sched Status
						* Read Only */
#define XUSBPS_IXR_AS_MASK	0x00008000 /**< Async Sched Status Read only */
#define XUSBPS_IXR_NAK_MASK	0x00010000 /**< NAK IRQ */
#define XUSBPS_IXR_UA_MASK	0x00040000 /**< USB Host Async IRQ */
#define XUSBPS_IXR_UP_MASK	0x00080000 /**< USB Host Periodic IRQ */
#define XUSBPS_IXR_TI0_MASK	0x01000000 /**< Timer 0 Interrupt */
#define XUSBPS_IXR_TI1_MASK	0x02000000 /**< Timer 1 Interrupt */

#define XUSBPS_IXR_ALL			(XUSBPS_IXR_UI_MASK	| \
					 XUSBPS_IXR_UE_MASK		| \
					 XUSBPS_IXR_PC_MASK	| \
					 XUSBPS_IXR_FRE_MASK	| \
					 XUSBPS_IXR_AA_MASK	| \
					 XUSBPS_IXR_UR_MASK		| \
					 XUSBPS_IXR_SR_MASK		| \
					 XUSBPS_IXR_SLE_MASK	| \
					 XUSBPS_IXR_ULPI_MASK		| \
					 XUSBPS_IXR_HCH_MASK	| \
					 XUSBPS_IXR_RCL_MASK	| \
					 XUSBPS_IXR_PS_MASK | \
					 XUSBPS_IXR_AS_MASK		| \
					 XUSBPS_IXR_NAK_MASK		| \
					 XUSBPS_IXR_UA_MASK	| \
					 XUSBPS_IXR_UP_MASK | \
					 XUSBPS_IXR_TI0_MASK | \
					 XUSBPS_IXR_TI1_MASK)
					/**< Mask for ALL IRQ types */
/* @} */


/** @name USB Mode Register (MODE) bit positions.
 *  @{
 */
#define XUSBPS_MODE_CM_MASK		0x00000003 /**< Controller Mode Select */
#define XUSBPS_MODE_CM_IDLE_MASK	0x00000000
#define XUSBPS_MODE_CM_DEVICE_MASK	0x00000002
#define XUSBPS_MODE_CM_HOST_MASK	0x00000003
#define XUSBPS_MODE_ES_MASK		0x00000004 /**< USB Endian Select */
#define XUSBPS_MODE_SLOM_MASK		0x00000008 /**< USB Setup Lockout Mode Disable */
#define XUSBPS_MODE_SDIS_MASK		0x00000010
#define XUSBPS_MODE_VALID_MASK		0x0000001F

/* @} */


/** @name USB Device Address Register (DEVICEADDR) bit positions.
 *  @{
 */
#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK	0x01000000
					/**< Device Addr Auto Advance */
#define XUSBPS_DEVICEADDR_ADDR_MASK		0xFE000000
					/**< Device Address */
#define XUSBPS_DEVICEADDR_ADDR_SHIFT		25
					/**< Address shift */
#define XUSBPS_DEVICEADDR_MAX			127
					/**< Biggest allowed address */
/* @} */

/** @name USB TT Control Register (TTCTRL) bit positions.
 *  @{
 */
#define XUSBPS_TTCTRL_HUBADDR_MASK	0x7F000000 /**< TT Hub Address */
/* @} */


/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
 *  @{
 */
#define XUSBPS_BURSTSIZE_RX_MASK	0x000000FF /**< RX Burst Length */
#define XUSBPS_BURSTSIZE_TX_MASK	0x0000FF00 /**< TX Burst Length */
/* @} */


/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
 *  @{
 */
#define XUSBPS_TXFILL_OVERHEAD_MASK	0x000000FF
					/**< Scheduler Overhead */
#define XUSBPS_TXFILL_HEALTH_MASK	0x00001F00
					/**< Scheduler Health Cntr */
#define XUSBPS_TXFILL_BURST_MASK	0x003F0000
					/**< FIFO Burst Threshold */
/* @} */


/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
 *  @{
 */
#define XUSBPS_ULPIVIEW_DATWR_MASK	0x000000FF /**< ULPI Data Write */
#define XUSBPS_ULPIVIEW_DATRD_MASK	0x0000FF00 /**< ULPI DATA Read */
#define XUSBPS_ULPIVIEW_ADDR_MASK	0x00FF0000 /**< ULPI Data Address */
#define XUSBPS_ULPIVIEW_SS_MASK	0x08000000 /**< ULPI Sync State */
#define XUSBPS_ULPIVIEW_RW_MASK	0x20000000 /**< ULPI R/W Ctrl */
#define XUSBPS_ULPIVIEW_RUN_MASK	0x40000000 /**< ULPI R/W Run */
#define XUSBPS_ULPIVIEW_WU_MASK	0x80000000 /**< ULPI Wakeup */
/* @} */


/** @name Port Status Control Register bit positions.
 *  @{
 */
#define XUSBPS_PORTSCR_CCS_MASK  0x00000001 /**< Current Connect Status */
#define XUSBPS_PORTSCR_CSC_MASK  0x00000002 /**< Connect Status Change */
#define XUSBPS_PORTSCR_PE_MASK	  0x00000004 /**< Port Enable/Disable */
#define XUSBPS_PORTSCR_PEC_MASK  0x00000008 /**< Port Enable/Disable Change */
#define XUSBPS_PORTSCR_OCA_MASK  0x00000010 /**< Over-current Active */
#define XUSBPS_PORTSCR_OCC_MASK  0x00000020 /**< Over-current Change */
#define XUSBPS_PORTSCR_FPR_MASK  0x00000040 /**< Force Port Resume */
#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
#define XUSBPS_PORTSCR_PR_MASK	  0x00000100 /**< Port Reset */
#define XUSBPS_PORTSCR_HSP_MASK  0x00000200 /**< High Speed Port */
#define XUSBPS_PORTSCR_LS_MASK	  0x00000C00 /**< Line Status */
#define XUSBPS_PORTSCR_PP_MASK	  0x00001000 /**< Port Power */
#define XUSBPS_PORTSCR_PO_MASK	  0x00002000 /**< Port Owner */
#define XUSBPS_PORTSCR_PIC_MASK  0x0000C000 /**< Port Indicator Control */
#define XUSBPS_PORTSCR_PTC_MASK  0x000F0000 /**< Port Test Control */
#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
						* Clock Disable */
#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
						* Connect */
#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
/* @} */


/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
 *  @{
 */
#define XUSBPS_OTGSC_VD_MASK	 0x00000001 /**< VBus Discharge Bit */
#define XUSBPS_OTGSC_VC_MASK	 0x00000002 /**< VBus Charge Bit */
#define XUSBPS_OTGSC_HAAR_MASK	 0x00000004 /**< HW Assist Auto Reset
				 		       *  Enable Bit */
#define XUSBPS_OTGSC_OT_MASK	 0x00000008 /**< OTG Termination Bit */
#define XUSBPS_OTGSC_DP_MASK	 0x00000010 /**< Data Pulsing Pull-up
				 		       *  Enable Bit */
#define XUSBPS_OTGSC_IDPU_MASK	 0x00000020 /**< ID Pull-up Enable Bit */
#define XUSBPS_OTGSC_HADP_MASK	 0x00000040 /**< HW Assist Data Pulse
							* Enable Bit */
#define XUSBPS_OTGSC_HABA_MASK	 0x00000080 /**< USB Hardware Assist
						       *  B Disconnect to A
						       *  Connect Enable Bit */
#define XUSBPS_OTGSC_ID_MASK	 0x00000100 /**< ID Status Flag */
#define XUSBPS_OTGSC_AVV_MASK	 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
#define XUSBPS_OTGSC_ASV_MASK	 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
#define XUSBPS_OTGSC_BSV_MASK	 0x00000800 /**< USB B Session Valid Status Flag */
#define XUSBPS_OTGSC_BSE_MASK	 0x00001000 /**< USB B Session End Status Flag */
#define XUSBPS_OTGSC_1MST_MASK	 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
#define XUSBPS_OTGSC_DPS_MASK	 0x00004000 /**< Data Pulse Status Flag */
#define XUSBPS_OTGSC_IDIS_MASK	 0x00010000 /**< USB ID Interrupt Status Flag */
#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
#define XUSBPS_OTGSC_1MSS_MASK	 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
#define XUSBPS_OTGSC_DPIS_MASK	 0x00400000 /**< Data Pulse Interrupt Status Flag */
#define XUSBPS_OTGSC_IDIE_MASK	 0x01000000 /**< ID Interrupt Enable Bit */
#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
#define XUSBPS_OTGSC_BSEE_MASK	 0x10000000 /**< USB B Session End Interrupt Enable Bit */
#define XUSBPS_OTGSC_1MSE_MASK	 0x20000000 /**< 1 Millisecond Timer
						* Interrupt Enable Bit */
#define XUSBPS_OTGSC_DPIE_MASK	 0x40000000 /**< Data Pulse Interrupt
							* Enable Bit */

#define XUSBPS_OTG_ISB_ALL	(XUSBPS_OTGSC_IDIS_MASK |\
				XUSBPS_OTGSC_AVVIS_MASK | \
				XUSBPS_OTGSC_ASVIS_MASK | \
				XUSBPS_OTGSC_BSVIS_MASK | \
				XUSBPS_OTGSC_BSEIS_MASK | \
				XUSBPS_OTGSC_1MSS_MASK | \
				XUSBPS_OTGSC_DPIS_MASK)
				/** Mask for All IRQ status masks */

#define XUSBPS_OTG_IEB_ALL	(XUSBPS_OTGSC_IDIE_MASK |\
				XUSBPS_OTGSC_AVVIE_MASK | \
				XUSBPS_OTGSC_ASVIE_MASK | \
				XUSBPS_OTGSC_BSVIE_MASK | \
				XUSBPS_OTGSC_BSEE_IEB_MASK | \
				XUSBPS_OTGSC_1MSE_MASK | \
				XUSBPS_OTGSC_DPIE_MASK)
				/** Mask for All IRQ Enable masks */
/* @} */


/**< Alignment of the Device Queue Head List BASE. */
#define XUSBPS_dQH_BASE_ALIGN		2048

/**< Alignment of a Device Queue Head structure. */
#define XUSBPS_dQH_ALIGN		64

/**< Alignment of a Device Transfer Descriptor structure. */
#define XUSBPS_dTD_ALIGN		32

/**< Size of one RX buffer for a OUT Transfer Descriptor. */
#define XUSBPS_dTD_BUF_SIZE		4096

/**< Maximum size of one RX/TX buffer. */
#define XUSBPS_dTD_BUF_MAX_SIZE	16*1024

/**< Alignment requirement for Transfer Descriptor buffers. */
#define XUSBPS_dTD_BUF_ALIGN		4096


/**************************** Type Definitions *******************************/

/***************** Macros (Inline Functions) Definitions *********************/

/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param	BaseAddress is the base address for the USB registers.
* @param	RegOffset is the register offset to be read.
*
* @return	The 32-bit value of the register.
*
* @note		C-style signature:
*		u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
				Xil_In32(BaseAddress + (RegOffset))


/****************************************************************************/
/**
*
* This macro writes the given register.
*
* @param	BaseAddress is the the base address for the USB registers.
* @param	RegOffset is the register offset to be written.
* @param	Data is the the 32-bit value to write to the register.
*
* @return	None.
*
* @note		C-style signature:
*		void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
 *****************************************************************************/
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
				Xil_Out32(BaseAddress + (RegOffset), (Data))


/************************** Function Prototypes ******************************/

/************************** Variable Definitions ******************************/

#ifdef __cplusplus
}
#endif

#endif /* XUSBPS_L_H */