xusbps_hw.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

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/**
 *
 * @file xusbps_hw.h
 *
 * This header file contains identifiers and low-level driver functions (or
 * macros) that can be used to access the device. High-level driver functions
 * are defined in xusbps.h.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a wgr  10/10/10 First release
 * </pre>
 *
 ******************************************************************************/
#ifndef XUSBPS_HW_H
#define XUSBPS_HW_H

#ifdef __cplusplus
extern "C" {
#endif

/***************************** Include Files *********************************/

#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"

/************************** Constant Definitions *****************************/


#define XUSBPS_REG_SPACING		4

/** @name Timer 0 Register offsets
 *
 * @{
 */
#define XUSBPS_TIMER0_LD_OFFSET	0x00000080
#define XUSBPS_TIMER0_CTL_OFFSET	0x00000084
/* @} */

/** @name Timer Control Register bit mask
 *
 * @{
 */
#define XUSBPS_TIMER_RUN_MASK		0x80000000
#define XUSBPS_TIMER_STOP_MASK		0x80000000
#define XUSBPS_TIMER_RESET_MASK	0x40000000
#define XUSBPS_TIMER_REPEAT_MASK	0x01000000
/* @} */

/** @name Timer Control Register bit mask
 *
 * @{
 */
#define XUSBPS_TIMER_COUNTER_MASK	0x00FFFFFF
/* @} */

/** @name Device Hardware Parameters
 *
 * @{
 */
#define XUSBPS_HWDEVICE_OFFSET		0x0000000C

#define XUSBPS_EP_NUM_MASK		0x3E
#define XUSBPS_EP_NUM_SHIFT		1
/* @} */

/** @name Capability Regsiter offsets
 */
#define XUSBPS_HCSPARAMS_OFFSET		0x00000104

/** @name Operational Register offsets.
 * Register comments are tagged with "H:" and "D:" for Host and Device modes,
 * respectively.
 * Tags are only present for registers that have a different meaning DEVICE and
 * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
 * Those registers don't have tags.
 * @{
 */
#define XUSBPS_CMD_OFFSET		0x00000140 /**< Configuration */
#define XUSBPS_ISR_OFFSET		0x00000144 /**< Interrupt Status */
#define XUSBPS_IER_OFFSET		0x00000148 /**< Interrupt Enable */
#define XUSBPS_FRAME_OFFSET		0x0000014C /**< USB Frame Index */
#define XUSBPS_LISTBASE_OFFSET		0x00000154 /**< H: Periodic List Base Address */
#define XUSBPS_DEVICEADDR_OFFSET	0x00000154 /**< D: Device Address */
#define XUSBPS_ASYNCLISTADDR_OFFSET	0x00000158 /**< H: Async List Address */
#define XUSBPS_EPLISTADDR_OFFSET	0x00000158 /**< D: Endpoint List Addr */
#define XUSBPS_TTCTRL_OFFSET		0x0000015C /**< TT Control */
#define XUSBPS_BURSTSIZE_OFFSET	0x00000160 /**< Burst Size */
#define XUSBPS_TXFILL_OFFSET		0x00000164 /**< Tx Fill Tuning */
#define XUSBPS_ULPIVIEW_OFFSET		0x00000170 /**< ULPI Viewport */
#define XUSBPS_EPNAKISR_OFFSET		0x00000178 /**< Endpoint NAK IRQ Status */
#define XUSBPS_EPNAKIER_OFFSET		0x0000017C /**< Endpoint NAK IRQ Enable */
#define XUSBPS_PORTSCR1_OFFSET		0x00000184 /**< Port Control/Status 1 */

/* NOTE: The Port Control / Status Register index is 1-based. */
#define XUSBPS_PORTSCRn_OFFSET(n)	\
		(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))


#define XUSBPS_OTGCSR_OFFSET	0x000001A4 /**< OTG Status and Control */
#define XUSBPS_MODE_OFFSET	0x000001A8 /**< USB Mode */
#define XUSBPS_EPSTAT_OFFSET	0x000001AC /**< Endpoint Setup Status */
#define XUSBPS_EPPRIME_OFFSET	0x000001B0 /**< Endpoint Prime */
#define XUSBPS_EPFLUSH_OFFSET	0x000001B4 /**< Endpoint Flush */
#define XUSBPS_EPRDY_OFFSET	0x000001B8 /**< Endpoint Ready */
#define XUSBPS_EPCOMPL_OFFSET	0x000001BC /**< Endpoint Complete */
#define XUSBPS_EPCR0_OFFSET	0x000001C0 /**< Endpoint Control 0 */
#define XUSBPS_EPCR1_OFFSET	0x000001C4 /**< Endpoint Control 1 */
#define XUSBPS_EPCR2_OFFSET	0x000001C8 /**< Endpoint Control 2 */
#define XUSBPS_EPCR3_OFFSET	0x000001CC /**< Endpoint Control 3 */
#define XUSBPS_EPCR4_OFFSET	0x000001D0 /**< Endpoint Control 4 */

#define XUSBPS_MAX_ENDPOINTS	4	   /**< Number of supported Endpoints in
					     *  this core. */
#define XUSBPS_EP_OUT_MASK	0x0000001F /**< OUR (RX) endpoint mask */
#define XUSBPS_EP_IN_MASK	0x001F0000 /**< IN (TX) endpoint mask */
#define XUSBPS_EP_ALL_MASK	0x001F001F /**< Mask used for endpoint control
					     *  registers */
#define XUSBPS_EPCRn_OFFSET(n)	\
		(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))

#define  XUSBPS_EPFLUSH_RX_SHIFT   0
#define  XUSBPS_EPFLUSH_TX_SHIFT  16

/* @} */



/** @name Endpoint Control Register (EPCR) bit positions.
 *  @{
 */

/* Definitions for TX Endpoint bits */
#define XUSBPS_EPCR_TXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - TX */
#define XUSBPS_EPCR_TXT_ISO_MASK	0x00040000 /**< Isochronous. Endpoint */
#define XUSBPS_EPCR_TXT_BULK_MASK	0x00080000 /**< Bulk Endpoint - TX */
#define XUSBPS_EPCR_TXT_INTR_MASK	0x000C0000 /**< Interrupt Endpoint */
#define XUSBPS_EPCR_TXS_MASK		0x00010000 /**< Stall TX endpoint */
#define XUSBPS_EPCR_TXE_MASK		0x00800000 /**< Transmit enable  - TX */
#define XUSBPS_EPCR_TXR_MASK		0x00400000 /**< Data Toggle Reset Bit */


/* Definitions for RX Endpoint bits */
#define XUSBPS_EPCR_RXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - RX */
#define XUSBPS_EPCR_RXT_ISO_MASK	0x00000004 /**< Isochronous Endpoint */
#define XUSBPS_EPCR_RXT_BULK_MASK	0x00000008 /**< Bulk Endpoint - RX */
#define XUSBPS_EPCR_RXT_INTR_MASK	0x0000000C /**< Interrupt Endpoint */
#define XUSBPS_EPCR_RXS_MASK		0x00000001 /**< Stall RX endpoint. */
#define XUSBPS_EPCR_RXE_MASK		0x00000080 /**< Transmit enable. - RX */
#define XUSBPS_EPCR_RXR_MASK		0x00000040 /**< Data Toggle Reset Bit */
/* @} */


/** @name USB Command Register (CR) bit positions.
 *  @{
 */
#define XUSBPS_CMD_RS_MASK	0x00000001 /**< Run/Stop */
#define XUSBPS_CMD_RST_MASK	0x00000002 /**< Controller RESET */
#define XUSBPS_CMD_FS01_MASK	0x0000000C /**< Frame List Size bit 0,1 */
#define XUSBPS_CMD_PSE_MASK	0x00000010 /**< Periodic Sched Enable */
#define XUSBPS_CMD_ASE_MASK	0x00000020 /**< Async Sched Enable */
#define XUSBPS_CMD_IAA_MASK	0x00000040 /**< IRQ Async Advance Doorbell */
#define XUSBPS_CMD_ASP_MASK	0x00000300 /**< Async Sched Park Mode Cnt */
#define XUSBPS_CMD_ASPE_MASK	0x00000800 /**< Async Sched Park Mode Enbl */
#define XUSBPS_CMD_SUTW_MASK	0x00002000 /**< Setup TripWire */
#define XUSBPS_CMD_ATDTW_MASK	0x00004000 /**< Add dTD TripWire */
#define XUSBPS_CMD_FS2_MASK	0x00008000 /**< Frame List Size bit 2 */
#define XUSBPS_CMD_ITC_MASK	0x00FF0000 /**< IRQ Threshold Control */
/* @} */


/**
 * @name Interrupt Threshold
 * These definitions are used by software to set the maximum rate at which the
 * USB controller will generate interrupt requests. The interrupt interval is
 * given in number of micro-frames.
 *
 * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
 * packet each and every 1ms. USB also defines a high-speed micro-frame with a
 * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
 * generated. Data is sent in between the SOF packets. The interrupt threshold
 * defines how many micro-frames the controller waits before issuing an
 * interrupt after data has been received.
 *
 * For a threshold of 0 the controller will issue an interrupt immediately
 * after the last byte of the data has been received. For a threshold n>0 the
 * controller will wait for n micro-frames before issuing an interrupt.
 *
 * Therefore, a setting of 8 micro-frames (default) means that the controller
 * will issue at most 1 interrupt per millisecond.
 *
 * @{
 */
#define XUSBPS_CMD_ITHRESHOLD_0	0x00 /**< Immediate interrupt. */
#define XUSBPS_CMD_ITHRESHOLD_1	0x01 /**< 1 micro-frame */
#define XUSBPS_CMD_ITHRESHOLD_2	0x02 /**< 2 micro-frames */
#define XUSBPS_CMD_ITHRESHOLD_4	0x04 /**< 4 micro-frames */
#define XUSBPS_CMD_ITHRESHOLD_8	0x08 /**< 8 micro-frames */
#define XUSBPS_CMD_ITHRESHOLD_16	0x10 /**< 16 micro-frames */
#define XUSBPS_CMD_ITHRESHOLD_32	0x20 /**< 32 micro-frames */
#define XUSBPS_CMD_ITHRESHOLD_64	0x40 /**< 64 micro-frames */
#define XUSBPS_CMD_ITHRESHOLD_MAX	XUSBPS_CMD_ITHRESHOLD_64
#define XUSBPS_CMD_ITHRESHOLD_DEFAULT	XUSBPS_CMD_ITHRESHOLD_8
/* @} */



/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
 * bit positions.
 *  @{
 */
#define XUSBPS_IXR_UI_MASK	0x00000001 /**< USB Transaction Complete */
#define XUSBPS_IXR_UE_MASK	0x00000002 /**< Transaction Error */
#define XUSBPS_IXR_PC_MASK	0x00000004 /**< Port Change Detect */
#define XUSBPS_IXR_FRE_MASK	0x00000008 /**< Frame List Rollover */
#define XUSBPS_IXR_AA_MASK	0x00000020 /**< Async Advance */
#define XUSBPS_IXR_UR_MASK	0x00000040 /**< RESET Received */
#define XUSBPS_IXR_SR_MASK	0x00000080 /**< Start of Frame */