xpm_counter.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

 * speculatively executed, and even more approximate of the total number of
 * instructions architecturally executed. The approximation depends mainly on
 * the branch misprediction rate.
 * The renaming stage can handle two instructions in the same cycle so the event
 * is two bits long:
 *    - b00 no instructions renamed
 *    - b01 one instruction renamed
 *    - b10 two instructions renamed
 */
#define XPM_EVENT_INSTRRENAME 0x68

/*
 * Counts the number of procedure returns whose condition codes do not fail,
 * excluding all returns from exception. This count includes procedure returns
 * which are flushed due to a previous load/store which aborts late.
 * Only the following instructions are reported:
 * - BX R14
 * - MOV PC LR
 * - POP {..,pc}
 * - LDR pc,[sp],#offset
 * The following instructions are not reported:
 * - LDMIA R9!,{..,PC} (ThumbEE state only)
 * - LDR PC,[R9],#offset (ThumbEE state only)
 * - BX R0 (Rm != R14)
 * - MOV PC,R0 (Rm != R14)
 * - LDM SP,{...,PC} (writeback not specified)
 * - LDR PC,[SP,#offset] (wrong addressing mode)
 */
#define XPM_EVENT_PREDICTFUNCRET 0x6E

/*
 * Counts the number of instructions being executed in the main execution
 * pipeline of the processor, the multiply pipeline and arithmetic logic unit
 * pipeline. The counted instructions are still speculative
 */
#define XPM_EVENT_MAINEXEC 0x70

/*
 * Counts the number of instructions being executed in the processor second
 * execution pipeline (ALU). The counted instructions are still speculative
 */
#define XPM_EVENT_SECEXEC 0x71

/*
 * Counts the number of instructions being executed in the Load/Store unit. The
 * counted instructions are still speculative
 */
#define XPM_EVENT_LDRSTR 0x72

/*
 * Counts the number of Floating-point instructions going through the Register
 * Rename stage. Instructions are still speculative in this stage.
 *Two floating-point instructions can be renamed in the same cycle so the event
 * is two bitslong:
 *0b00 no floating-point instruction renamed
 *0b01 one floating-point instruction renamed
 *0b10 two floating-point instructions renamed
 */
#define XPM_EVENT_FLOATRENAME 0x73

/*
 * Counts the number of Neon instructions going through the Register Rename
 * stage.Instructions are still speculative in this stage.
 * Two NEON instructions can be renamed in the same cycle so the event is two
 * bits long:
 *0b00 no NEON instruction renamed
 *0b01 one NEON instruction renamed
 *0b10 two NEON instructions renamed
 */
#define XPM_EVENT_NEONRENAME 0x74

/*
 * Counts the number of cycles where the processor is stalled because PLD slots
 * are all full
 */
#define XPM_EVENT_PLDSTALL 0x80

/*
 * Counts the number of cycles when the processor is stalled and the data side
 * is stalled too because it is full and executing writes to the external
 * memory
 */
#define XPM_EVENT_WRITESTALL 0x81

/*
 * Counts the number of stall cycles due to main TLB misses on requests issued
 * by the instruction side
 */
#define XPM_EVENT_INSTRTLBSTALL 0x82

/*
 * Counts the number of stall cycles due to main TLB misses on requests issued
 * by the data side
 */
#define XPM_EVENT_DATATLBSTALL 0x83

/*
 * Counts the number of stall cycles due to micro TLB misses on the instruction
 * side. This event does not include main TLB miss stall cycles that are already
 * counted in the corresponding main TLB event
 */
#define XPM_EVENT_INSTR_uTLBSTALL 0x84

/*
 * Counts the number of stall cycles due to micro TLB misses on the data side.
 * This event does not include main TLB miss stall cycles that are already
 * counted in the corresponding main TLB event
 */
#define XPM_EVENT_DATA_uTLBSTALL 0x85

/*
 * Counts the number of stall cycles because of the execution of a DMB memory
 * barrier. This includes all DMB instructions being executed, even
 * speculatively
 */
#define XPM_EVENT_DMB_STALL 0x86

/*
 * Counts the number of cycles during which the integer core clock is enabled
 */
#define XPM_EVENT_INT_CLKEN 0x8A

/*
 * Counts the number of cycles during which the Data Engine clock is enabled
 */
#define XPM_EVENT_DE_CLKEN 0x8B

/*
 * Counts the number of ISB instructions architecturally executed
 */
#define XPM_EVENT_INSTRISB 0x90

/*
 * Counts the number of DSB instructions architecturally executed
 */
#define XPM_EVENT_INSTRDSB 0x91

/*
 * Counts the number of DMB instructions speculatively executed
 */
#define XPM_EVENT_INSTRDMB 0x92

/*
 * Counts the number of external interrupts executed by the processor
 */
#define XPM_EVENT_EXTINT 0x93

/*
 * PLE cache line request completed
 */
#define XPM_EVENT_PLE_LRC 0xA0

/*
 * PLE cache line request skipped
 */
#define XPM_EVENT_PLE_LRS 0xA1

/*
 * PLE FIFO flush
 */
#define XPM_EVENT_PLE_FLUSH 0xA2

/*
 * PLE request complete
 */
#define XPM_EVENT_PLE_CMPL 0xA3

/*
 * PLE FIFO overflow
 */
#define XPM_EVENT_PLE_OVFL 0xA4

/*
 * PLE request programmed
 */
#define XPM_EVENT_PLE_PROG 0xA5

/*
 * The following constants define the configurations for Cortex-A9 Performance
 * Monitor Events. Each configuration configures the event counters for a set
 * of events.
 * -----------------------------------------------
 * Config		PmCtr0... PmCtr5
 * -----------------------------------------------
 * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
 *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
 *			  XPM_EVENT_INSTRFECT_TLBREFILL,
 *			  XPM_EVENT_DATA_CACHEREFILL,
 *			  XPM_EVENT_DATA_CACHEACCESS,
 *			  XPM_EVENT_DATA_TLBREFILL }
 *
 * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
 *			  XPM_EVENT_DATA_WRITE,
 *			  XPM_EVENT_EXCEPTION,
 *			  XPM_EVENT_EXCEPRETURN,
 *			  XPM_EVENT_CHANGECONTEXT,
 *			  XPM_EVENT_SW_CHANGEPC }
 *
 * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
 *			  XPM_EVENT_UNALIGNEDACCESS,
 *			  XPM_EVENT_BRANCHMISS,
 *			  XPM_EVENT_CLOCKCYCLES,
 *			  XPM_EVENT_BRANCHPREDICT,
 *			  XPM_EVENT_JAVABYTECODE }
 *
 * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
 *			  XPM_EVENT_JAVABACKBRANCH,
 *			  XPM_EVENT_COHERLINEMISS,
 *			  XPM_EVENT_COHERLINEHIT,
 *			  XPM_EVENT_INSTRSTALL,
 *			  XPM_EVENT_DATASTALL }
 *
 * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
 *			  XPM_EVENT_STREXPASS,
 *			  XPM_EVENT_STREXFAIL,
 *			  XPM_EVENT_DATAEVICT,
 *			  XPM_EVENT_NODISPATCH,
 *			  XPM_EVENT_ISSUEEMPTY }
 *
 * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
 *			  XPM_EVENT_PREDICTFUNCRET,
 *			  XPM_EVENT_MAINEXEC,
 *			  XPM_EVENT_SECEXEC,
 *			  XPM_EVENT_LDRSTR,
 *			  XPM_EVENT_FLOATRENAME }
 *
 * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
 *			  XPM_EVENT_PLDSTALL,
 *			  XPM_EVENT_WRITESTALL,
 *			  XPM_EVENT_INSTRTLBSTALL,
 *			  XPM_EVENT_DATATLBSTALL,
 *			  XPM_EVENT_INSTR_uTLBSTALL }
 *
 * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
 *			  XPM_EVENT_DMB_STALL,
 *			  XPM_EVENT_INT_CLKEN,
 *			  XPM_EVENT_DE_CLKEN,
 *			  XPM_EVENT_INSTRISB,
 *			  XPM_EVENT_INSTRDSB }
 *
 * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
 *			  XPM_EVENT_EXTINT,
 *			  XPM_EVENT_PLE_LRC,
 *			  XPM_EVENT_PLE_LRS,
 *			  XPM_EVENT_PLE_FLUSH,
 *			  XPM_EVENT_PLE_CMPL }
 *
 * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
 *			  XPM_EVENT_PLE_PROG,
 *			  XPM_EVENT_PLE_LRC,
 *			  XPM_EVENT_PLE_LRS,
 *			  XPM_EVENT_PLE_FLUSH,
 *			  XPM_EVENT_PLE_CMPL }
 *
 * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
 *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
 *			  XPM_EVENT_INSTRFECT_TLBREFILL,
 *			  XPM_EVENT_DATA_CACHEREFILL,
 *			  XPM_EVENT_DATA_CACHEACCESS,
 *			  XPM_EVENT_DATA_TLBREFILL }
 */
#define XPM_CNTRCFG1	0
#define XPM_CNTRCFG2	1
#define XPM_CNTRCFG3	2
#define XPM_CNTRCFG4	3
#define XPM_CNTRCFG5	4
#define XPM_CNTRCFG6	5
#define XPM_CNTRCFG7	6
#define XPM_CNTRCFG8	7
#define XPM_CNTRCFG9	8
#define XPM_CNTRCFG10	9
#define XPM_CNTRCFG11	10

/**************************** Type Definitions ******************************/

/***************** Macros (Inline Functions) Definitions ********************/

/************************** Variable Definitions ****************************/

/************************** Function Prototypes *****************************/

/* Interface fuctions to access perfromance counters from abstraction layer */
void Xpm_SetEvents(int PmcrCfg);
void Xpm_GetEventCounters(u32 *PmCtrValue);

#ifdef __cplusplus
}
#endif

#endif