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📄 translation_table.s

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/* $Id: translation_table.s,v 1.1.4.1 2011/10/24 09:35:19 sadanan Exp $*//******************************************************************************** (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.** This file contains confidential and proprietary information of Xilinx, Inc.* and is protected under U.S. and international copyright and other* intellectual property laws.** DISCLAIMER* This disclaimer is not a license and does not grant any rights to the* materials distributed herewith. Except as otherwise provided in a valid* license issued to you by Xilinx, and to the maximum extent permitted by* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;* and (2) Xilinx shall not be liable (whether in contract or tort, including* negligence, or under any other theory of liability) for any loss or damage* of any kind or nature related to, arising under or in connection with these* materials, including for any direct, or any indirect, special, incidental,* or consequential loss or damage (including loss of data, profits, goodwill,* or any type of loss or damage suffered as a result of any action brought by* a third party) even if such damage or loss was reasonably foreseeable or* Xilinx had been advised of the possibility of the same.** CRITICAL APPLICATIONS* Xilinx products are not designed or intended to be fail-safe, or for use in* any application requiring fail-safe performance, such as life-support or* safety devices or systems, Class III medical devices, nuclear facilities,* applications related to the deployment of airbags, or any other applications* that could lead to death, personal injury, or severe property or* environmental damage (individually and collectively, "Critical* Applications"). Customer assumes the sole risk and liability of any use of* Xilinx products in Critical Applications, subject only to applicable laws* and regulations governing limitations on product liability.** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE* AT ALL TIMES.*******************************************************************************//*****************************************************************************//*** @file translation_table.s** This file contains the initialization for the MMU table in RAM* needed by the Cortex A9 processor** <pre>* MODIFICATION HISTORY:** Ver   Who  Date     Changes* ----- ---- -------- ---------------------------------------------------* 1.00a ecm  10/20/09 Initial version* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable* </pre>** @note** None.*******************************************************************************/	.globl  MMUTable	.section .mmu_tbl,"aS"MMUTable:	/* Each table entry occupies one 32-bit word and there are	 * 4096 entries, so the entire table takes up 16KB.	 * Each entry covers a 1MB section.	 */.set SECT, 0.rept	0x0400			/* 0x00000000 - 0x3fffffff (DDR Cacheable) */.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */.set	SECT, SECT+0x100000.endr.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0200			/* 0xc0000000 - 0xdfffffff (unassigned/reserved).				 * Generates a translation fault if accessed */.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0020			/* 0xe0000000 - 0xe1ffffff (Memory mapped devices)				 * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0020			/* 0xe2000000 - 0xe3ffffff (NOR) */.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0020			/* 0xe4000000 - 0xe5ffffff (SRAM) */.word	SECT + 0xc0e		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */.set	SECT, SECT+0x100000.endr.rept	0x0120			/* 0xe6000000 - 0xf7ffffff (unassigned/reserved).				 * Generates a translation fault if accessed */.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0010			/* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */.word	SECT + 0xc02		/* S=b0 TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x0030			/* 0xf9000000 - 0xfbffffff (unassigned/reserved).				 * Generates a translation fault if accessed */.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */.set	SECT, SECT+0x100000.endr.rept	0x003f			/* 0xfc000000 - 0xffefffff (Linear QSPI - XIP) */.word	SECT + 0xc0a		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */.set	SECT, SECT+0x100000.endr				/* 256K OCM when mapped to high address space				 * inner-cacheable */.word	SECT + 0x4c0e		/* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */.set	SECT, SECT+0x100000.end

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