xil_macroback.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

/*********************************************************************/
/**
 * (c) Copyright 2010 Xilinx, Inc. All rights reserved.
 * 
 * This file contains confidential and proprietary information
 * of Xilinx, Inc. and is protected under U.S. and
 * international copyright and other intellectual property
 * laws.
 * 
 * DISCLAIMER
 * This disclaimer is not a license and does not grant any
 * rights to the materials distributed herewith. Except as
 * otherwise provided in a valid license issued to you by
 * Xilinx, and to the maximum extent permitted by applicable
 * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 * (2) Xilinx shall not be liable (whether in contract or tort,
 * including negligence, or under any other theory of
 * liability) for any loss or damage of any kind or nature
 * related to, arising under or in connection with these
 * materials, including for any direct, or any indirect,
 * special, incidental, or consequential loss or damage
 * (including loss of data, profits, goodwill, or any type of
 * loss or damage suffered as a result of any action brought
 * by a third party) even if such damage or loss was
 * reasonably foreseeable or Xilinx had been advised of the
 * possibility of the same.
 * 
 * CRITICAL APPLICATIONS
 * Xilinx products are not designed or intended to be fail-
 * safe, or for use in any application requiring fail-safe
 * performance, such as life-support or safety devices or
 * systems, Class III medical devices, nuclear facilities,
 * applications related to the deployment of airbags, or any
 * other applications that could lead to death, personal
 * injury, or severe property or environmental damage
 * (individually and collectively, "Critical
 * Applications"). Customer assumes the sole risk and
 * liability of any use of Xilinx products in Critical
 * Applications, subject only to applicable laws and
 * regulations governing limitations on product liability.
 * 
 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 * PART OF THIS FILE AT ALL TIMES.
 *********************************************************************/

/*********************************************************************/
/**
 * @file xil_macroback.h
 * 
 * This header file is meant to bring back the removed _m macros.
 * This header file must be included last.
 * The following macros are not defined here due to the driver change:
 *   XGpio_mSetDataDirection
 *   XGpio_mGetDataReg
 *   XGpio_mSetDataReg
 *   XIIC_RESET
 *   XIIC_CLEAR_STATS
 *   XSpi_mReset
 *   XSysAce_mSetCfgAddr
 *   XSysAce_mIsCfgDone
 *   XTft_mSetPixel
 *   XTft_mGetPixel
 *   XWdtTb_mEnableWdt
 *   XWdtTb_mDisbleWdt
 *   XWdtTb_mRestartWdt
 *   XWdtTb_mGetTimebaseReg
 *   XWdtTb_mHasReset
 * 
 * Please refer the corresonding driver document for replacement.
 * 
 *********************************************************************/

#ifndef XIL_MACROBACK_H
#define XIL_MACROBACK_H

/*********************************************************************/
/**
 * Macros for Driver XCan
 * 
 *********************************************************************/
#ifndef XCan_mReadReg
#define XCan_mReadReg XCan_ReadReg
#endif

#ifndef XCan_mWriteReg
#define XCan_mWriteReg XCan_WriteReg
#endif

#ifndef XCan_mIsTxDone
#define XCan_mIsTxDone XCan_IsTxDone
#endif

#ifndef XCan_mIsTxFifoFull
#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
#endif

#ifndef XCan_mIsHighPriorityBufFull
#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
#endif

#ifndef XCan_mIsRxEmpty
#define XCan_mIsRxEmpty XCan_IsRxEmpty
#endif

#ifndef XCan_mIsAcceptFilterBusy
#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
#endif

#ifndef XCan_mCreateIdValue
#define XCan_mCreateIdValue XCan_CreateIdValue
#endif

#ifndef XCan_mCreateDlcValue
#define XCan_mCreateDlcValue XCan_CreateDlcValue
#endif

/*********************************************************************/
/**
 * Macros for Driver XDmaCentral
 * 
 *********************************************************************/
#ifndef XDmaCentral_mWriteReg
#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
#endif

#ifndef XDmaCentral_mReadReg
#define XDmaCentral_mReadReg XDmaCentral_ReadReg
#endif

/*********************************************************************/
/**
 * Macros for Driver XDsAdc
 * 
 *********************************************************************/
#ifndef XDsAdc_mWriteReg
#define XDsAdc_mWriteReg XDsAdc_WriteReg
#endif

#ifndef XDsAdc_mReadReg
#define XDsAdc_mReadReg XDsAdc_ReadReg
#endif

#ifndef XDsAdc_mIsEmpty
#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
#endif

#ifndef XDsAdc_mSetFstmReg
#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
#endif

#ifndef XDsAdc_mGetFstmReg
#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
#endif

#ifndef XDsAdc_mEnableConversion
#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
#endif

#ifndef XDsAdc_mDisableConversion
#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
#endif

#ifndef XDsAdc_mGetFifoOccyReg
#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
#endif

/*********************************************************************/
/**
 * Macros for Driver XDsDac
 * 
 *********************************************************************/
#ifndef XDsDac_mWriteReg
#define XDsDac_mWriteReg XDsDac_WriteReg
#endif

#ifndef XDsDac_mReadReg
#define XDsDac_mReadReg XDsDac_ReadReg
#endif

#ifndef XDsDac_mIsEmpty
#define XDsDac_mIsEmpty XDsDac_IsEmpty
#endif

#ifndef XDsDac_mFifoIsFull
#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
#endif

#ifndef XDsDac_mGetVacancy
#define XDsDac_mGetVacancy XDsDac_GetVacancy
#endif

/*********************************************************************/
/**
 * Macros for Driver XEmacLite
 * 
 *********************************************************************/
#ifndef XEmacLite_mReadReg
#define XEmacLite_mReadReg XEmacLite_ReadReg
#endif

#ifndef XEmacLite_mWriteReg
#define XEmacLite_mWriteReg XEmacLite_WriteReg
#endif

#ifndef XEmacLite_mGetTxStatus
#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
#endif

#ifndef XEmacLite_mSetTxStatus
#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
#endif

#ifndef XEmacLite_mGetRxStatus
#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
#endif

#ifndef XEmacLite_mSetRxStatus
#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
#endif

#ifndef XEmacLite_mIsTxDone
#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
#endif

#ifndef XEmacLite_mIsRxEmpty
#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
#endif

#ifndef XEmacLite_mNextTransmitAddr
#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
#endif

#ifndef XEmacLite_mNextReceiveAddr
#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
#endif

#ifndef XEmacLite_mIsMdioConfigured
#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
#endif

#ifndef XEmacLite_mIsLoopbackConfigured
#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
#endif

#ifndef XEmacLite_mGetReceiveDataLength
#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
#endif

#ifndef XEmacLite_mGetTxActive
#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
#endif

#ifndef XEmacLite_mSetTxActive
#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
#endif

/*********************************************************************/
/**
 * Macros for Driver XGpio
 * 
 *********************************************************************/
#ifndef XGpio_mWriteReg
#define XGpio_mWriteReg XGpio_WriteReg
#endif

#ifndef XGpio_mReadReg
#define XGpio_mReadReg XGpio_ReadReg
#endif

/*********************************************************************/
/**
 * Macros for Driver XHwIcap
 * 
 *********************************************************************/
#ifndef XHwIcap_mFifoWrite
#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
#endif

#ifndef XHwIcap_mFifoRead
#define XHwIcap_mFifoRead XHwIcap_FifoRead
#endif

#ifndef XHwIcap_mSetSizeReg
#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
#endif

#ifndef XHwIcap_mGetControlReg
#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
#endif

#ifndef XHwIcap_mStartConfig
#define XHwIcap_mStartConfig XHwIcap_StartConfig
#endif

#ifndef XHwIcap_mStartReadBack
#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
#endif

#ifndef XHwIcap_mGetStatusReg
#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
#endif

#ifndef XHwIcap_mIsTransferDone
#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
#endif

#ifndef XHwIcap_mIsDeviceBusy
#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
#endif

#ifndef XHwIcap_mIntrGlobalEnable
#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
#endif

#ifndef XHwIcap_mIntrGlobalDisable
#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
#endif

#ifndef XHwIcap_mIntrGetStatus
#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
#endif

#ifndef XHwIcap_mIntrDisable
#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
#endif

#ifndef XHwIcap_mIntrEnable
#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
#endif

#ifndef XHwIcap_mIntrGetEnabled
#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
#endif

#ifndef XHwIcap_mIntrClear
#define XHwIcap_mIntrClear XHwIcap_IntrClear
#endif

#ifndef XHwIcap_mGetWrFifoVacancy
#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
#endif

#ifndef XHwIcap_mGetRdFifoOccupancy
#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
#endif

#ifndef XHwIcap_mSliceX2Col
#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
#endif

#ifndef XHwIcap_mSliceY2Row
#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
#endif

#ifndef XHwIcap_mSliceXY2Slice
#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
#endif

#ifndef XHwIcap_mReadReg
#define XHwIcap_mReadReg XHwIcap_ReadReg
#endif

#ifndef XHwIcap_mWriteReg
#define XHwIcap_mWriteReg XHwIcap_WriteReg
#endif

/*********************************************************************/
/**
 * Macros for Driver XIic
 * 
 *********************************************************************/
#ifndef XIic_mReadReg
#define XIic_mReadReg XIic_ReadReg
#endif

#ifndef XIic_mWriteReg
#define XIic_mWriteReg XIic_WriteReg
#endif

#ifndef XIic_mEnterCriticalRegion
#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
#endif

#ifndef XIic_mExitCriticalRegion
#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
#endif

#ifndef XIIC_GINTR_DISABLE
#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
#endif

#ifndef XIIC_GINTR_ENABLE
#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
#endif

#ifndef XIIC_IS_GINTR_ENABLED
#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
#endif

#ifndef XIIC_WRITE_IISR
#define XIIC_WRITE_IISR XIic_WriteIisr
#endif

#ifndef XIIC_READ_IISR
#define XIIC_READ_IISR XIic_ReadIisr
#endif

#ifndef XIIC_WRITE_IIER
#define XIIC_WRITE_IIER XIic_WriteIier
#endif

#ifndef XIic_mClearIisr
#define XIic_mClearIisr XIic_ClearIisr
#endif

#ifndef XIic_mSend7BitAddress
#define XIic_mSend7BitAddress XIic_Send7BitAddress
#endif

#ifndef XIic_mDynSend7BitAddress
#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
#endif

#ifndef XIic_mDynSendStartStopAddress
#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
#endif

#ifndef XIic_mDynSendStop
#define XIic_mDynSendStop XIic_DynSendStop
#endif

#ifndef XIic_mSend10BitAddrByte1
#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
#endif

#ifndef XIic_mSend10BitAddrByte2
#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
#endif

#ifndef XIic_mSend7BitAddr
#define XIic_mSend7BitAddr XIic_Send7BitAddr
#endif

#ifndef XIic_mDisableIntr
#define XIic_mDisableIntr XIic_DisableIntr
#endif

#ifndef XIic_mEnableIntr
#define XIic_mEnableIntr XIic_EnableIntr
#endif

#ifndef XIic_mClearIntr
#define XIic_mClearIntr XIic_ClearIntr
#endif

#ifndef XIic_mClearEnableIntr
#define XIic_mClearEnableIntr XIic_ClearEnableIntr
#endif

#ifndef XIic_mFlushRxFifo
#define XIic_mFlushRxFifo XIic_FlushRxFifo
#endif

#ifndef XIic_mFlushTxFifo
#define XIic_mFlushTxFifo XIic_FlushTxFifo
#endif

#ifndef XIic_mReadRecvByte
#define XIic_mReadRecvByte XIic_ReadRecvByte
#endif

#ifndef XIic_mWriteSendByte
#define XIic_mWriteSendByte XIic_WriteSendByte
#endif

#ifndef XIic_mSetControlRegister
#define XIic_mSetControlRegister XIic_SetControlRegister
#endif

/*********************************************************************/
/**
 * Macros for Driver XIntc
 * 
 *********************************************************************/
#ifndef XIntc_mMasterEnable
#define XIntc_mMasterEnable XIntc_MasterEnable
#endif

#ifndef XIntc_mMasterDisable
#define XIntc_mMasterDisable XIntc_MasterDisable
#endif

#ifndef XIntc_mEnableIntr
#define XIntc_mEnableIntr XIntc_EnableIntr
#endif

#ifndef XIntc_mDisableIntr
#define XIntc_mDisableIntr XIntc_DisableIntr
#endif

#ifndef XIntc_mAckIntr
#define XIntc_mAckIntr XIntc_AckIntr
#endif

#ifndef XIntc_mGetIntrStatus
#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
#endif

/*********************************************************************/
/**
 * Macros for Driver XLlDma
 * 
 *********************************************************************/
#ifndef XLlDma_mBdRead
#define XLlDma_mBdRead XLlDma_BdRead
#endif

#ifndef XLlDma_mBdWrite
#define XLlDma_mBdWrite XLlDma_BdWrite
#endif

#ifndef XLlDma_mWriteReg
#define XLlDma_mWriteReg XLlDma_WriteReg
#endif

#ifndef XLlDma_mReadReg
#define XLlDma_mReadReg XLlDma_ReadReg
#endif

#ifndef XLlDma_mBdClear
#define XLlDma_mBdClear XLlDma_BdClear