xparameters.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

*/
#define XPAR_PLB2OPB_0_NUM_MASTERS       1         /* Number of masters on bus
*/


/*****************************************************************************
 *
 * OPB To PLB Bridge defines.
 * DeviceID starts at 150
 */
#define XPAR_XOPB2PLB_NUM_INSTANCES     1
#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF       /* Accessible from OPB, not DCR */

#define XPAR_OPB2PLB_0_DEVICE_ID       150   /* Device ID for instance */
#define XPAR_OPB2PLB_0_OPB_BASEADDR    0x0   /* Register base address */
#define XPAR_OPB2PLB_0_DCR_BASEADDR    0x0   /* DCR Register base address */


/*****************************************************************************
 *
 * System ACE defines.
 * DeviceID starts at 160
 */
#define XPAR_XSYSACE_NUM_INSTANCES    1

#define XPAR_SYSACE_0_DEVICE_ID       160         /* Device ID for instance */
#define XPAR_SYSACE_0_BASEADDR        0xCF000000  /* Register base address */


/*****************************************************************************
 *
 * HDLC defines.
 * DeviceID starts at 170
 */
#define XPAR_XHDLC_NUM_INSTANCES     1

#define XPAR_HDLC_0_DEVICE_ID       170             /* Device ID for instance */
#define XPAR_HDLC_0_BASEADDR        0x60010000      /* Register base address */
#define XPAR_HDLC_0_TX_MEM_DEPTH    2048            /* Tx FIFO depth (bytes) */
#define XPAR_HDLC_0_RX_MEM_DEPTH    2048            /* Rx FIFO depth (bytes) */
#define XPAR_HDLC_0_DMA_PRESENT     3               /* DMA SG in hardware */


/*****************************************************************************
 *
 * PS2 Reference driver defines.
 * DeviceID starts at 180
 */
#define XPAR_XPS2_NUM_INSTANCES    2

#define XPAR_PS2_0_DEVICE_ID       180             /* Device ID for instance */
#define XPAR_PS2_0_BASEADDR        0x40010000      /* Register base address */

#define XPAR_PS2_1_DEVICE_ID       181             /* Device ID for instance */
#define XPAR_PS2_1_BASEADDR        0x40020000      /* Register base address */

/*****************************************************************************
 *
 * Rapid IO defines.
 * DeviceID starts at 190
 */
#define XPAR_XRAPIDIO_NUM_INSTANCES    1

#define XPAR_RAPIDIO_0_DEVICE_ID       190             /* Device ID for instance */
#define XPAR_RAPIDIO_0_BASEADDR        0x60000000      /* Register base address */


/*****************************************************************************
 *
 * PCI defines.
 * DeviceID starts at 200
 */
#define XPAR_XPCI_NUM_INSTANCES                      1
#define XPAR_OPB_PCI_1_DEVICE_ID                     200
#define XPAR_OPB_PCI_1_BASEADDR                      0x86000000
#define XPAR_OPB_PCI_1_HIGHADDR                      0x860001FF
#define XPAR_OPB_PCI_1_PCIBAR_0                      0x10000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_0                  27
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0                 0xF0000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0  0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_0                1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0               1
#define XPAR_OPB_PCI_1_PCIBAR_1                      0x3F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_1                  15
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1                 0xC0FF8000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1  0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_1                1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1               1
#define XPAR_OPB_PCI_1_PCIBAR_2                      0x5F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_2                  16
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2                 0x00000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2  0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_2                1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2               1
#define XPAR_OPB_PCI_1_IPIFBAR_0                     0x80000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0               0x81FFFFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0                 0xF0000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0              1
#define XPAR_OPB_PCI_1_IPIFBAR_1                     0x82000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1               0x820007FF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1                 0xCE000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1              1
#define XPAR_OPB_PCI_1_IPIFBAR_2                     0x82320000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2               0x8232FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2              1
#define XPAR_OPB_PCI_1_IPIFBAR_3                     0x82330000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3               0x8233FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3              0
#define XPAR_OPB_PCI_1_IPIFBAR_4                     0x82340000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4               0x8234FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4               0
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4              0
#define XPAR_OPB_PCI_1_IPIFBAR_5                     0x82350000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5               0x8235FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5              1
#define XPAR_OPB_PCI_1_DMA_BASEADDR                  0x87000000
#define XPAR_OPB_PCI_1_DMA_HIGHADDR                  0x8700007F
#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE                 0
#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH              11

/*****************************************************************************
 *
 * GEmac defines.
 * DeviceID starts at 210
 */
#define XPAR_XGEMAC_NUM_INSTANCES    1
#define XPAR_GEMAC_0_DEVICE_ID       210
#define XPAR_GEMAC_0_BASEADDR        0x61000000
#define XPAR_GEMAC_0_DMA_TYPE        9
#define XPAR_GEMAC_0_MIIM_EXIST      0
#define XPAR_GEMAC_0_INCLUDE_STATS   0


/*****************************************************************************
 *
 * Touchscreen defines .
 * DeviceID starts at 220
 */
#define XPAR_XTOUCHSCREEN_NUM_INSTANCES  1
#define XPAR_TOUCHSCREEN_0_DEVICE_ID     220
#define XPAR_TOUCHSCREEN_0_BASEADDR      0x70000000


/*****************************************************************************
 *
 * DDR defines .
 * DeviceID starts at 230
 */
#define XPAR_XDDR_NUM_INSTANCES         1
#define XPAR_DDR_0_DEVICE_ID            230
#define XPAR_DDR_0_BASEADDR             0
#define XPAR_DDR_0_INTERRUPT_PRESENT    0

/*****************************************************************************
 *
 * EmacLite defines .
 * DeviceID starts at 240
 */
#define XPAR_XEMACLITE_NUM_INSTANCES    1
#define XPAR_EMACLITE_0_DEVICE_ID       240
#define XPAR_EMACLITE_0_BASEADDR        0
#define XPAR_EMACLITE_0_TX_PING_PONG    0
#define XPAR_EMACLITE_0_RX_PING_PONG    0

/*****************************************************************************
 *
 * DSDAC defines .
 * DeviceID starts at 250
 */
#define XPAR_XDSDAC_NUM_INSTANCES       1
#define XPAR_DSDAC_0_DEVICE_ID          250
#define XPAR_DSDAC_0_BASEADDR           0

/*****************************************************************************
 *
 * DSADC defines .
 * DeviceID starts at 260
 */
#define XPAR_XDSADC_NUM_INSTANCES       1
#define XPAR_DSADC_0_DEVICE_ID          260
#define XPAR_DSADC_0_BASEADDR           0

/*****************************************************************************
 *
 * PCI Arbiter defines.
 * DeviceID starts at 270
 */
#define XPAR_XPCIARB_NUM_INSTANCES     1
#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID     270
#define XPAR_OPB_PCI_ARBITER_0_BASEADDR      0
#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2

/*****************************************************************************
 *
 * TEMAC defines .
 * DeviceID starts at 280
 */
#define XPAR_XTEMAC_NUM_INSTANCES       1
#define XPAR_TEMAC_0_DEVICE_ID          280
#define XPAR_TEMAC_0_BASEADDR           0
#define XPAR_TEMAC_0_DMA_TYPE        3
#define XPAR_TEMAC_0_RDFIFO_DEPTH    131072
#define XPAR_TEMAC_0_WRFIFO_DEPTH    131072
#define XPAR_TEMAC_0_MAC_FIFO_DEPTH  16
#define XPAR_TEMAC_0_TEMAC_DCR_HOST  0
#define XPAR_TEMAC_0_DRE             0

/*****************************************************************************
 *
 * DMACENTRAL defines .
 * DeviceID starts at 290
 */
#define XPAR_XDMACENTRAL_NUM_INSTANCES       1
#define XPAR_DMACENTRAL_0_DEVICE_ID          290
#define XPAR_DMACENTRAL_0_BASEADDR           0
#define XPAR_DMACENTRAL_0_READ_OPTIONAL_REGS 0

/*****************************************************************************
 *
 * CAN defines
 * DeviceID starts at 300
 */
#define XPAR_XCAN_NUM_INSTANCES  1
#define XPAR_CAN_0_DEVICE_ID     300

/* Definitions for FLEXRAY Driver */
#define XPAR_XFLEXRAY_NUM_INSTANCES 1
#define XPAR_OPB_FLEXRAY_0_DEVICE_ID    0
#define XPAR_OPB_FLEXRAY_0_BASEADDR  0x7D80E000
#define XPAR_OPB_FLEXRAY_MAX_PAYLOAD_SIZE 254
#define XPAR_OPB_FLEXRAY_NO_OF_TX_BUFFERS   128
#define XPAR_OPB_FLEXRAY_NO_OF_RX_BUFFERS   128
#define XPAR_OPB_FLEXRAY_RX_FIFO_DEPTH      16

/* Definitions for MOST driver */
#define XPAR_XMOST_NUM_INSTANCES 1
#define XPAR_MOST_0_DEVICE_ID 0
#define XPAR_MOST_0_BASEADDR 0x7D810000
#define XPAR_MOST_OPMODE	0
#define XPAR_MOST_FWC 16
#define XPAR_MOST_EWC 16

/* Definitions for USB driver */
#define XPAR_XUSB_NUM_INSTANCES	1
#define XPAR_USB_0_DEVICE_ID	0
#define XPAR_USB_0_BASEADDR	0x7D813000

/*****************************************************************************
 *
 * HWICAP defines .
 */
#define XPAR_XHWICAP_NUM_INSTANCES       1
#define XPAR_OPB_HWICAP_0_DEVICE_ID      0
#define XPAR_OPB_HWICAP_0_BASEADDR        0xFFFFFFFF

/*****************************************************************************
 *
 * LLTEMAC and LLFIFO defines .
 */
#define XPAR_XLLTEMAC_NUM_INSTANCES      1
#define XPAR_XLLFIFO_NUM_INSTANCES       1

/*****************************************************************************
 *
 * PCIe defines .
 */
#define XPAR_XPCIE_NUM_INSTANCES       1

/*****************************************************************************
 *
 * MPMC defines .
 */
#define XPAR_XMPMC_NUM_INSTANCES         1

/*****************************************************************************
 *
 * SYSMON defines .
 */
#define XPAR_XSYSMON_NUM_INSTANCES         1


/*****************************************************************************
 *
 * AXI Ethernet defines .
 */
#define XPAR_XAXIETHERNET_NUM_INSTANCES         1

/*****************************************************************************
 *
 * TFT defines .
 */
#define XPAR_XTFT_NUM_INSTANCES		1

/*****************************************************************************
 *
 * MBox defines .
 */
#define XPAR_XMBOX_NUM_INSTANCES         	1
#define XPAR_XMBOX_0_DEVICE_ID				0
#define XPAR_XMBOX_0_BASEADDR				0x7D814000
#define XPAR_XMBOX_0_NUM_CHANNELS			1
#define XPAR_XMBOX_0_USE_FSL				0


/*****************************************************************************
 *
 * Mutex defines .
 */
#define XPAR_XMUTEX_NUM_INSTANCES         	1
#define XPAR_XMUTEX_0_DEVICE_ID				0
#define XPAR_XMUTEX_0_BASEADDR				0x7D815000
#define XPAR_XMUTEX_0_NUM_MUTEX				2
#define XPAR_XMUTEX_0_ENABLE_USER			1

/*
 * MicroBlaze sets this define but for the build check to
 * function it needs to be set here
 */
#define XPAR_CPU_ID 0


/*****************************************************************************
 *
 * BRAM defines .
 */
#define XPAR_XBRAM_NUM_INSTANCES         	1


/*****************************************************************************
 *
 * AXI PCIE defines .
 */
#define XPAR_XAXIPCIE_NUM_INSTANCES         	1

/*****************************************************************************
 *
 * V6 DDRX efines .
 */
#define XPAR_XV6DDR_NUM_INSTANCES         	1


/**************************** Type Definitions *******************************/


/***************** Macros (Inline Functions) Definitions *********************/

#ifdef __cplusplus
}
#endif

#endif              /* end of protection macro */