xcanps.c

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

	/*
	 * Read Error Counter Register and parse it.
	 */
	ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_ECR_OFFSET);
	*RxErrorCount = (ErrorCount & XCANPS_ECR_REC_MASK) >>
				XCANPS_ECR_REC_SHIFT;
	*TxErrorCount = ErrorCount & XCANPS_ECR_TEC_MASK;
}

/*****************************************************************************/
/**
*
* This function reads Error Status value from Error Status Register (ESR). Use
* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the
* returned value.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
*
* @return	The 32-bit value read from Error Status Register.
*
* @note		None.
*
******************************************************************************/
u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr)
{

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_ESR_OFFSET);
}

/*****************************************************************************/
/**
*
* This function clears Error Status bit(s) previously set in Error
* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h
* to create the value to pass in. If a bit was cleared in Error Status Register
* before this function is called, it will not be modified.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
*
* @param	Mask is he 32-bit mask used to clear bits in Error Status
*		Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear
*		multiple bits.
*
* @note		None.
*
******************************************************************************/
void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask)
{
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_ESR_OFFSET, Mask);
}

/*****************************************************************************/
/**
*
* This function sends a CAN Frame. If the TX FIFO is not full then the given
* frame is written into the the TX FIFO otherwise, it returns an error code
* immediately.
* This function does not wait for the given frame being sent to CAN bus.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
* @param	FramePtr is a pointer to a 32-bit aligned buffer containing the
*		CAN frame to be sent.
*
* @return
*		- XST_SUCCESS if TX FIFO was not full and the given frame was
*		written into the FIFO.
*		- XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the
*		given frame.
*
* @note		None.
*
******************************************************************************/
int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(FramePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) {
		return XST_FIFO_NO_ROOM;
	}

	/*
	 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
	 */
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXFIFO_DW1_OFFSET, FramePtr[2]);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXFIFO_DW2_OFFSET, FramePtr[3]);

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This function receives a CAN Frame. This function first checks if RX FIFO is
* empty, if not, it then reads a frame from the RX FIFO into the given buffer.
* This function returns error code immediately if there is no frame in the RX
* FIFO.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
* @param	FramePtr is a pointer to a 32-bit aligned buffer where the CAN
*		frame to be written.
*
* @return
*		- XST_SUCCESS if RX FIFO was not empty and a frame was read from
*		RX FIFO successfully and written into the given buffer.
*		- XST_NO_DATA if there is no frame to be received from the FIFO.
*
* @note		None.
*
******************************************************************************/
int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(FramePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) {
		return XST_NO_DATA;
	}

	/*
	 * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device.
	 */
	FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
					XCANPS_RXFIFO_ID_OFFSET);
	FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
					XCANPS_RXFIFO_DLC_OFFSET);
	FramePtr[2] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
					XCANPS_RXFIFO_DW1_OFFSET);
	FramePtr[3] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
					XCANPS_RXFIFO_DW2_OFFSET);

	/*
	 * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call
	 * returns correct RX FIFO occupancy/empty condition.
	 */
	XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK);

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This routine sends a CAN High Priority frame. This function first checks if
* TX High Priority Buffer is empty. If yes, it then writes the given frame into
* the Buffer. If not, this function returns immediately. This function does not
* wait for the given frame being sent to CAN bus.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
* @param	FramePtr is a pointer to a 32-bit aligned buffer containing the
*		CAN High Priority frame to be sent.
*
* @return
*		- XST_SUCCESS if TX High Priority Buffer was not full and the
*		given frame was written into the buffer;
*		- XST_FIFO_NO_ROOM if there is no room in the TX High Priority
*		Buffer for this frame.
*
* @note
*
* If the frame needs to be sent immediately and not delayed by processor's
* interrupt handling, the caller should disable interrupt at processor
* level before invoking this function.
*
******************************************************************************/
int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(FramePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) {
		return XST_FIFO_NO_ROOM;
	}

	/*
	 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
	 */
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXHPB_ID_OFFSET, FramePtr[0]);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXHPB_DW1_OFFSET, FramePtr[2]);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
			XCANPS_TXHPB_DW2_OFFSET, FramePtr[3]);

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This routine enables individual acceptance filters. Up to 4 filters could
* be enabled.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
* @param	FilterIndexes specifies which filter(s) to enable. Use
*		any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or"
*		multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
*		to be enabled. Any filter not specified in this parameter will
*		keep its previous enable/disable setting.
*
* @return	None.
*
* @note		None.
*
*
******************************************************************************/
void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes)
{
	u32 EnabledFilters;

	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 *  Calculate the new value and write to AFR.
	 */
	EnabledFilters =  XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
						XCANPS_AFR_OFFSET);
	EnabledFilters |= FilterIndexes;
	EnabledFilters &= XCANPS_AFR_UAF_ALL_MASK;
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
			EnabledFilters);
}

/*****************************************************************************/
/**
*
* This routine disables individual acceptance filters. Up to 4 filters could
* be disabled. If all acceptance filters are disabled then all the received
* frames are stored in the RX FIFO.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
* @param	FilterIndexes specifies which filter(s) to disable. Use
*		any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or"
*		multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
* 		to be disabled. Any filter not specified in this parameter will
*		keep its previous enable/disable setting. If all acceptance
*		filters are disabled then all received frames are stored in the
*		RX FIFO.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes)
{
	u32 EnabledFilters;

	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 *  Calculate the new value and write to AFR.
	 */
	EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
					XCANPS_AFR_OFFSET);
	EnabledFilters &= XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes);
	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
			   EnabledFilters);
}

/*****************************************************************************/
/**
*
* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK
* defined in xcanps_hw.h to interpret the returned value. If no acceptance
* filters are enabled then all received frames are stored in the RX FIFO.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
*
* @return	The value stored in Acceptance Filter Register.
*
* @note		None.
*
*
******************************************************************************/
u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr)
{

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFR_OFFSET);

}

/*****************************************************************************/
/**
*
* This function sets values to the Acceptance Filter Mask Register (AFMR) and
* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the
* filter. Read the xcanps.h file and device specification for details.
*
* This function should be called only after:
*   - The given filter is disabled by calling XCanPs_AcceptFilterDisable();
*   - And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
*	 XCanPs_IsAcceptFilterBusy() returns FALSE.
*
* @param	InstancePtr is a pointer to the XCanPs instance.
* @param	FilterIndex defines which Acceptance Filter Mask and ID Register
*		to set. Use any single XCANPS_AFR_UAF*_MASK value.
* @param	MaskValue is the value to write to the chosen Acceptance Filter
*		Mask Register.
* @param	IdValue is the value to write to the chosen Acceptance Filter
*		ID Register.
*
* @return
*		- XST_SUCCESS if the values were set successfully.
*		- XST_FAILURE if the given filter was not disabled, or the CAN
*		device was not ready to accept writes to AFMR and AFIR.
*
* @note		None.
*
******************************************************************************/
int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
			 u32 MaskValue, u32 IdValue)
{
	u32 EnabledFilters;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
			(FilterIndex == XCANPS_AFR_UAF3_MASK) ||
			(FilterIndex == XCANPS_AFR_UAF2_MASK) ||
			(FilterIndex == XCANPS_AFR_UAF1_MASK));

	/*
	 * Return an error if the given filter is currently enabled.
	 */
	EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr);
	if ((EnabledFilters & FilterIndex) == FilterIndex) {
		return XST_FAILURE;
	}

	/*
	 * If the CAN device is not ready to accept writes to AFMR and AFIR,
	 * return error code.
	 */
	if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) {
		return XST_FAILURE;
	}

	/*
	 * Write to the AFMR and AFIR of the specified filter.
	 */
	switch (FilterIndex) {
	case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */

		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFMR1_OFFSET, MaskValue);
		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFIR1_OFFSET, IdValue);
		break;

	case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFMR2_OFFSET, MaskValue);
		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFIR2_OFFSET, IdValue);
		break;

	case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFMR3_OFFSET, MaskValue);
		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
				XCANPS_AFIR3_OFFSET, IdValue);