xcanps.h

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

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/**
*
* @file xcanps.h
*
* The Xilinx CAN driver component.  This component supports the Xilinx
* CAN Controller.
*
* The CAN Controller supports the following features:
*	- Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
*	- Supports both Standard (11 bit Identifier) and Extended (29 bit
*	  Identifier) frames.
*	- Supports Bit Rates up to 1 Mbps.
*	- Transmit message object FIFO with a user configurable depth of
*	  up to 64 message objects.
*	- Transmit prioritization through one TX High Priority Buffer.
*	- Receive message object FIFO with a user configurable depth of
*	  up to 64 message objects.
*	- Watermark interrupts for Rx FIFO with configurable Watermark.
*	- Acceptance filtering with 4 acceptance filters.
*	- Sleep mode with automatic wake up.
*	- Loop Back mode for diagnostic applications.
*	- Snoop mode for diagnostic applications.
*	- Maskable Error and Status Interrupts.
*	- Readable Error Counters.
*	- External PHY chip required.
*	- Receive Timestamp.
*
* The device driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the CAN. The driver handles transmission and reception of
* CAN frames, as well as configuration of the controller. The driver is simply a
* pass-through mechanism between a protocol stack and the CAN. A single device
* driver can support multiple CANs.
*
* Since the driver is a simple pass-through mechanism between a protocol stack
* and the CAN, no assembly or disassembly of CAN frames is done at the
* driver-level. This assumes that the protocol stack passes a correctly
* formatted CAN frame to the driver for transmission, and that the driver
* does not validate the contents of an incoming frame
*
* <b>Operation Modes</b>
*
* The CAN controller supports the following modes of operation:
*   - <b>Configuration Mode</b>: In this mode the CAN timing parameters and
*	 Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
*	 controller loses synchronization with the CAN bus and drives a
*	 constant recessive bit on the bus line. The Error Counter Register are
*	 reset. The CAN controller does not receive or transmit any messages
*	 even if there are pending transmit requests from the TX FIFO or the TX
*	 High Priority Buffer. The Storage FIFOs and the CAN configuration
*	 registers are still accessible.
*   - <b>Normal Mode</b>:In Normal Mode the CAN controller participates in bus
*	 communication, by transmitting and receiving messages.
*   - <b>Sleep Mode</b>: In Sleep Mode the CAN Controller does not transmit any
*	 messages. However, if any other node transmits a message, then the CAN
*	 Controller receives the transmitted message and exits from Sleep Mode.
*	 If there are new transmission requests from either the TX FIFO or the
*	 TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
*	 requests are not serviced, and the CAN Controller continues to remain
*	 in Sleep Mode. Interrupts are generated when the CAN controller enters
*	Sleep mode or Wakes up from Sleep mode.
*   - <b>Loop Back Mode</b>: In Loop Back mode, the CAN controller transmits a
*	 recessive bit stream on to the CAN Bus. Any message that is transmitted
*	 is looped back to the 慠x